1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
3*4882a593Smuzhiyun #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun * 32-bit hash table MMU support
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * BATs
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /* Block size masks */
14*4882a593Smuzhiyun #define BL_128K 0x000
15*4882a593Smuzhiyun #define BL_256K 0x001
16*4882a593Smuzhiyun #define BL_512K 0x003
17*4882a593Smuzhiyun #define BL_1M 0x007
18*4882a593Smuzhiyun #define BL_2M 0x00F
19*4882a593Smuzhiyun #define BL_4M 0x01F
20*4882a593Smuzhiyun #define BL_8M 0x03F
21*4882a593Smuzhiyun #define BL_16M 0x07F
22*4882a593Smuzhiyun #define BL_32M 0x0FF
23*4882a593Smuzhiyun #define BL_64M 0x1FF
24*4882a593Smuzhiyun #define BL_128M 0x3FF
25*4882a593Smuzhiyun #define BL_256M 0x7FF
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* BAT Access Protection */
28*4882a593Smuzhiyun #define BPP_XX 0x00 /* No access */
29*4882a593Smuzhiyun #define BPP_RX 0x01 /* Read only */
30*4882a593Smuzhiyun #define BPP_RW 0x02 /* Read/write */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #ifndef __ASSEMBLY__
33*4882a593Smuzhiyun /* Contort a phys_addr_t into the right format/bits for a BAT */
34*4882a593Smuzhiyun #ifdef CONFIG_PHYS_64BIT
35*4882a593Smuzhiyun #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
36*4882a593Smuzhiyun ((x & 0x0000000e00000000ULL) >> 24) | \
37*4882a593Smuzhiyun ((x & 0x0000000100000000ULL) >> 30)))
38*4882a593Smuzhiyun #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
39*4882a593Smuzhiyun (((u64)(x) << 24) & 0x0000000e00000000ULL) | \
40*4882a593Smuzhiyun (((u64)(x) << 30) & 0x0000000100000000ULL))
41*4882a593Smuzhiyun #else
42*4882a593Smuzhiyun #define BAT_PHYS_ADDR(x) (x)
43*4882a593Smuzhiyun #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct ppc_bat {
47*4882a593Smuzhiyun u32 batu;
48*4882a593Smuzhiyun u32 batl;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * Hash table
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Values for PP (assumes Ks=0, Kp=1) */
57*4882a593Smuzhiyun #define PP_RWXX 0 /* Supervisor read/write, User none */
58*4882a593Smuzhiyun #define PP_RWRX 1 /* Supervisor read/write, User read */
59*4882a593Smuzhiyun #define PP_RWRW 2 /* Supervisor read/write, User read/write */
60*4882a593Smuzhiyun #define PP_RXRX 3 /* Supervisor read, User read */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Values for Segment Registers */
63*4882a593Smuzhiyun #define SR_NX 0x10000000 /* No Execute */
64*4882a593Smuzhiyun #define SR_KP 0x20000000 /* User key */
65*4882a593Smuzhiyun #define SR_KS 0x40000000 /* Supervisor key */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifndef __ASSEMBLY__
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * Hardware Page Table Entry
71*4882a593Smuzhiyun * Note that the xpn and x bitfields are used only by processors that
72*4882a593Smuzhiyun * support extended addressing; otherwise, those bits are reserved.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun struct hash_pte {
75*4882a593Smuzhiyun unsigned long v:1; /* Entry is valid */
76*4882a593Smuzhiyun unsigned long vsid:24; /* Virtual segment identifier */
77*4882a593Smuzhiyun unsigned long h:1; /* Hash algorithm indicator */
78*4882a593Smuzhiyun unsigned long api:6; /* Abbreviated page index */
79*4882a593Smuzhiyun unsigned long rpn:20; /* Real (physical) page number */
80*4882a593Smuzhiyun unsigned long xpn:3; /* Real page number bits 0-2, optional */
81*4882a593Smuzhiyun unsigned long r:1; /* Referenced */
82*4882a593Smuzhiyun unsigned long c:1; /* Changed */
83*4882a593Smuzhiyun unsigned long w:1; /* Write-thru cache mode */
84*4882a593Smuzhiyun unsigned long i:1; /* Cache inhibited */
85*4882a593Smuzhiyun unsigned long m:1; /* Memory coherence */
86*4882a593Smuzhiyun unsigned long g:1; /* Guarded */
87*4882a593Smuzhiyun unsigned long x:1; /* Real page number bit 3, optional */
88*4882a593Smuzhiyun unsigned long pp:2; /* Page protection */
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun typedef struct {
92*4882a593Smuzhiyun unsigned long id;
93*4882a593Smuzhiyun unsigned long vdso_base;
94*4882a593Smuzhiyun } mm_context_t;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun void update_bats(void);
cleanup_cpu_mmu_context(void)97*4882a593Smuzhiyun static inline void cleanup_cpu_mmu_context(void) { };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* patch sites */
100*4882a593Smuzhiyun extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
101*4882a593Smuzhiyun extern s32 patch__hash_page_B, patch__hash_page_C;
102*4882a593Smuzhiyun extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
103*4882a593Smuzhiyun extern s32 patch__flush_hash_B;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun int __init find_free_bat(void);
106*4882a593Smuzhiyun unsigned int bat_block_size(unsigned long base, unsigned long top);
107*4882a593Smuzhiyun #endif /* !__ASSEMBLY__ */
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* We happily ignore the smaller BATs on 601, we don't actually use
110*4882a593Smuzhiyun * those definitions on hash32 at the moment anyway
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun #define mmu_virtual_psize MMU_PAGE_4K
113*4882a593Smuzhiyun #define mmu_linear_psize MMU_PAGE_256M
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #endif /* _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ */
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