1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Common registers for PPC AES implementation 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define rKS r0 /* copy of en-/decryption key pointer */ 9*4882a593Smuzhiyun #define rDP r3 /* destination pointer */ 10*4882a593Smuzhiyun #define rSP r4 /* source pointer */ 11*4882a593Smuzhiyun #define rKP r5 /* pointer to en-/decryption key pointer */ 12*4882a593Smuzhiyun #define rRR r6 /* en-/decryption rounds */ 13*4882a593Smuzhiyun #define rLN r7 /* length of data to be processed */ 14*4882a593Smuzhiyun #define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */ 15*4882a593Smuzhiyun #define rKT r9 /* pointer to tweak key (XTS mode) */ 16*4882a593Smuzhiyun #define rT0 r11 /* pointers to en-/decryption tables */ 17*4882a593Smuzhiyun #define rT1 r10 18*4882a593Smuzhiyun #define rD0 r9 /* data */ 19*4882a593Smuzhiyun #define rD1 r14 20*4882a593Smuzhiyun #define rD2 r12 21*4882a593Smuzhiyun #define rD3 r15 22*4882a593Smuzhiyun #define rW0 r16 /* working registers */ 23*4882a593Smuzhiyun #define rW1 r17 24*4882a593Smuzhiyun #define rW2 r18 25*4882a593Smuzhiyun #define rW3 r19 26*4882a593Smuzhiyun #define rW4 r20 27*4882a593Smuzhiyun #define rW5 r21 28*4882a593Smuzhiyun #define rW6 r22 29*4882a593Smuzhiyun #define rW7 r23 30*4882a593Smuzhiyun #define rI0 r24 /* IV */ 31*4882a593Smuzhiyun #define rI1 r25 32*4882a593Smuzhiyun #define rI2 r26 33*4882a593Smuzhiyun #define rI3 r27 34*4882a593Smuzhiyun #define rG0 r28 /* endian reversed tweak (XTS mode) */ 35*4882a593Smuzhiyun #define rG1 r29 36*4882a593Smuzhiyun #define rG2 r30 37*4882a593Smuzhiyun #define rG3 r31 38