1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PowerQUICC II support functions
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Scott Wood <scottwood@freescale.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2007 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "ops.h"
11*4882a593Smuzhiyun #include "types.h"
12*4882a593Smuzhiyun #include "fsl-soc.h"
13*4882a593Smuzhiyun #include "pq2.h"
14*4882a593Smuzhiyun #include "stdio.h"
15*4882a593Smuzhiyun #include "io.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
18*4882a593Smuzhiyun #define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static int pq2_corecnf_map[] = {
21*4882a593Smuzhiyun 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
22*4882a593Smuzhiyun 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Get various clocks from crystal frequency.
26*4882a593Smuzhiyun * Returns zero on failure and non-zero on success.
27*4882a593Smuzhiyun */
pq2_get_clocks(u32 crystal,u32 * sysfreq,u32 * corefreq,u32 * timebase,u32 * brgfreq)28*4882a593Smuzhiyun int pq2_get_clocks(u32 crystal, u32 *sysfreq, u32 *corefreq,
29*4882a593Smuzhiyun u32 *timebase, u32 *brgfreq)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun u32 *immr;
32*4882a593Smuzhiyun u32 sccr, scmr, mainclk, busclk;
33*4882a593Smuzhiyun int corecnf, busdf, plldf, pllmf, dfbrg;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun immr = fsl_get_immr();
36*4882a593Smuzhiyun if (!immr) {
37*4882a593Smuzhiyun printf("pq2_get_clocks: Couldn't get IMMR base.\r\n");
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun sccr = in_be32(&immr[PQ2_SCCR]);
42*4882a593Smuzhiyun scmr = in_be32(&immr[PQ2_SCMR]);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun dfbrg = sccr & 3;
45*4882a593Smuzhiyun corecnf = (scmr >> 24) & 0x1f;
46*4882a593Smuzhiyun busdf = (scmr >> 20) & 0xf;
47*4882a593Smuzhiyun plldf = (scmr >> 12) & 1;
48*4882a593Smuzhiyun pllmf = scmr & 0xfff;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun mainclk = crystal * (pllmf + 1) / (plldf + 1);
51*4882a593Smuzhiyun busclk = mainclk / (busdf + 1);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if (sysfreq)
54*4882a593Smuzhiyun *sysfreq = mainclk / 2;
55*4882a593Smuzhiyun if (timebase)
56*4882a593Smuzhiyun *timebase = busclk / 4;
57*4882a593Smuzhiyun if (brgfreq)
58*4882a593Smuzhiyun *brgfreq = mainclk / (1 << ((dfbrg + 1) * 2));
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (corefreq) {
61*4882a593Smuzhiyun int coremult = pq2_corecnf_map[corecnf];
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (coremult < 0)
64*4882a593Smuzhiyun *corefreq = mainclk / 2;
65*4882a593Smuzhiyun else if (coremult == 0)
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun else
68*4882a593Smuzhiyun *corefreq = busclk * coremult / 2;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 1;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Set common device tree fields based on the given clock frequencies. */
pq2_set_clocks(u32 sysfreq,u32 corefreq,u32 timebase,u32 brgfreq)75*4882a593Smuzhiyun void pq2_set_clocks(u32 sysfreq, u32 corefreq, u32 timebase, u32 brgfreq)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun void *node;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun dt_fixup_cpu_clocks(corefreq, timebase, sysfreq);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun node = finddevice("/soc/cpm");
82*4882a593Smuzhiyun if (node)
83*4882a593Smuzhiyun setprop(node, "clock-frequency", &sysfreq, 4);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun node = finddevice("/soc/cpm/brg");
86*4882a593Smuzhiyun if (node)
87*4882a593Smuzhiyun setprop(node, "clock-frequency", &brgfreq, 4);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
pq2_fixup_clocks(u32 crystal)90*4882a593Smuzhiyun int pq2_fixup_clocks(u32 crystal)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun u32 sysfreq, corefreq, timebase, brgfreq;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (!pq2_get_clocks(crystal, &sysfreq, &corefreq, &timebase, &brgfreq))
95*4882a593Smuzhiyun return 0;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun pq2_set_clocks(sysfreq, corefreq, timebase, brgfreq);
98*4882a593Smuzhiyun return 1;
99*4882a593Smuzhiyun }
100