1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This interface is used for compatibility with old U-boots *ONLY*. 4*4882a593Smuzhiyun * Please do not imitate or extend this. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * (C) Copyright 2000, 2001 9*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __PPCBOOT_H__ 13*4882a593Smuzhiyun #define __PPCBOOT_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Board information passed to kernel from PPCBoot 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * include/asm-ppc/ppcboot.h 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include "types.h" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun typedef struct bd_info { 24*4882a593Smuzhiyun unsigned long bi_memstart; /* start of DRAM memory */ 25*4882a593Smuzhiyun unsigned long bi_memsize; /* size of DRAM memory in bytes */ 26*4882a593Smuzhiyun unsigned long bi_flashstart; /* start of FLASH memory */ 27*4882a593Smuzhiyun unsigned long bi_flashsize; /* size of FLASH memory */ 28*4882a593Smuzhiyun unsigned long bi_flashoffset; /* reserved area for startup monitor */ 29*4882a593Smuzhiyun unsigned long bi_sramstart; /* start of SRAM memory */ 30*4882a593Smuzhiyun unsigned long bi_sramsize; /* size of SRAM memory */ 31*4882a593Smuzhiyun #if defined(TARGET_8xx) || defined(TARGET_CPM2) || defined(TARGET_85xx) ||\ 32*4882a593Smuzhiyun defined(TARGET_83xx) || defined(TARGET_86xx) 33*4882a593Smuzhiyun unsigned long bi_immr_base; /* base of IMMR register */ 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun #if defined(TARGET_PPC_MPC52xx) 36*4882a593Smuzhiyun unsigned long bi_mbar_base; /* base of internal registers */ 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ 39*4882a593Smuzhiyun unsigned long bi_ip_addr; /* IP Address */ 40*4882a593Smuzhiyun unsigned char bi_enetaddr[6]; /* Ethernet address */ 41*4882a593Smuzhiyun unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ 42*4882a593Smuzhiyun unsigned long bi_intfreq; /* Internal Freq, in MHz */ 43*4882a593Smuzhiyun unsigned long bi_busfreq; /* Bus Freq, in MHz */ 44*4882a593Smuzhiyun #if defined(TARGET_CPM2) 45*4882a593Smuzhiyun unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ 46*4882a593Smuzhiyun unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ 47*4882a593Smuzhiyun unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ 48*4882a593Smuzhiyun unsigned long bi_vco; /* VCO Out from PLL, in MHz */ 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun #if defined(TARGET_PPC_MPC52xx) 51*4882a593Smuzhiyun unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ 52*4882a593Smuzhiyun unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun unsigned long bi_baudrate; /* Console Baudrate */ 55*4882a593Smuzhiyun #if defined(TARGET_4xx) 56*4882a593Smuzhiyun unsigned char bi_s_version[4]; /* Version of this structure */ 57*4882a593Smuzhiyun unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */ 58*4882a593Smuzhiyun unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ 59*4882a593Smuzhiyun unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ 60*4882a593Smuzhiyun unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ 61*4882a593Smuzhiyun unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ 62*4882a593Smuzhiyun #endif 63*4882a593Smuzhiyun #if defined(TARGET_HYMOD) 64*4882a593Smuzhiyun hymod_conf_t bi_hymod_conf; /* hymod configuration information */ 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun #if defined(TARGET_EVB64260) || defined(TARGET_405EP) || defined(TARGET_44x) || \ 67*4882a593Smuzhiyun defined(TARGET_85xx) || defined(TARGET_83xx) || defined(TARGET_HAS_ETH1) 68*4882a593Smuzhiyun /* second onboard ethernet port */ 69*4882a593Smuzhiyun unsigned char bi_enet1addr[6]; 70*4882a593Smuzhiyun #define HAVE_ENET1ADDR 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun #if defined(TARGET_EVB64260) || defined(TARGET_440GX) || \ 73*4882a593Smuzhiyun defined(TARGET_85xx) || defined(TARGET_HAS_ETH2) 74*4882a593Smuzhiyun /* third onboard ethernet ports */ 75*4882a593Smuzhiyun unsigned char bi_enet2addr[6]; 76*4882a593Smuzhiyun #define HAVE_ENET2ADDR 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun #if defined(TARGET_440GX) || defined(TARGET_HAS_ETH3) 79*4882a593Smuzhiyun /* fourth onboard ethernet ports */ 80*4882a593Smuzhiyun unsigned char bi_enet3addr[6]; 81*4882a593Smuzhiyun #define HAVE_ENET3ADDR 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun #if defined(TARGET_4xx) 84*4882a593Smuzhiyun unsigned int bi_opbfreq; /* OB clock in Hz */ 85*4882a593Smuzhiyun int bi_iic_fast[2]; /* Use fast i2c mode */ 86*4882a593Smuzhiyun #endif 87*4882a593Smuzhiyun #if defined(TARGET_440GX) 88*4882a593Smuzhiyun int bi_phynum[4]; /* phy mapping */ 89*4882a593Smuzhiyun int bi_phymode[4]; /* phy mode */ 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun } bd_t; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define bi_tbfreq bi_intfreq 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif /* __PPCBOOT_H__ */ 96