1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef _PPC64_PPC_ASM_H 3*4882a593Smuzhiyun #define _PPC64_PPC_ASM_H 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Definitions used by various bits of low-level assembly code on PowerPC. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Condition Register Bit Fields */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define cr0 0 14*4882a593Smuzhiyun #define cr1 1 15*4882a593Smuzhiyun #define cr2 2 16*4882a593Smuzhiyun #define cr3 3 17*4882a593Smuzhiyun #define cr4 4 18*4882a593Smuzhiyun #define cr5 5 19*4882a593Smuzhiyun #define cr6 6 20*4882a593Smuzhiyun #define cr7 7 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* General Purpose Registers (GPRs) */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define r0 0 26*4882a593Smuzhiyun #define r1 1 27*4882a593Smuzhiyun #define r2 2 28*4882a593Smuzhiyun #define r3 3 29*4882a593Smuzhiyun #define r4 4 30*4882a593Smuzhiyun #define r5 5 31*4882a593Smuzhiyun #define r6 6 32*4882a593Smuzhiyun #define r7 7 33*4882a593Smuzhiyun #define r8 8 34*4882a593Smuzhiyun #define r9 9 35*4882a593Smuzhiyun #define r10 10 36*4882a593Smuzhiyun #define r11 11 37*4882a593Smuzhiyun #define r12 12 38*4882a593Smuzhiyun #define r13 13 39*4882a593Smuzhiyun #define r14 14 40*4882a593Smuzhiyun #define r15 15 41*4882a593Smuzhiyun #define r16 16 42*4882a593Smuzhiyun #define r17 17 43*4882a593Smuzhiyun #define r18 18 44*4882a593Smuzhiyun #define r19 19 45*4882a593Smuzhiyun #define r20 20 46*4882a593Smuzhiyun #define r21 21 47*4882a593Smuzhiyun #define r22 22 48*4882a593Smuzhiyun #define r23 23 49*4882a593Smuzhiyun #define r24 24 50*4882a593Smuzhiyun #define r25 25 51*4882a593Smuzhiyun #define r26 26 52*4882a593Smuzhiyun #define r27 27 53*4882a593Smuzhiyun #define r28 28 54*4882a593Smuzhiyun #define r29 29 55*4882a593Smuzhiyun #define r30 30 56*4882a593Smuzhiyun #define r31 31 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define SPRN_TBRL 268 59*4882a593Smuzhiyun #define SPRN_TBRU 269 60*4882a593Smuzhiyun #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 61*4882a593Smuzhiyun #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define MSR_LE 0x0000000000000001 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define FIXUP_ENDIAN \ 66*4882a593Smuzhiyun tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 67*4882a593Smuzhiyun b $+44; /* Skip trampoline if endian is good */ \ 68*4882a593Smuzhiyun .long 0xa600607d; /* mfmsr r11 */ \ 69*4882a593Smuzhiyun .long 0x01006b69; /* xori r11,r11,1 */ \ 70*4882a593Smuzhiyun .long 0x00004039; /* li r10,0 */ \ 71*4882a593Smuzhiyun .long 0x6401417d; /* mtmsrd r10,1 */ \ 72*4882a593Smuzhiyun .long 0x05009f42; /* bcl 20,31,$+4 */ \ 73*4882a593Smuzhiyun .long 0xa602487d; /* mflr r10 */ \ 74*4882a593Smuzhiyun .long 0x14004a39; /* addi r10,r10,20 */ \ 75*4882a593Smuzhiyun .long 0xa6035a7d; /* mtsrr0 r10 */ \ 76*4882a593Smuzhiyun .long 0xa6037b7d; /* mtsrr1 r11 */ \ 77*4882a593Smuzhiyun .long 0x2400004c /* rfid */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifdef CONFIG_PPC_8xx 80*4882a593Smuzhiyun #define MFTBL(dest) mftb dest 81*4882a593Smuzhiyun #define MFTBU(dest) mftbu dest 82*4882a593Smuzhiyun #else 83*4882a593Smuzhiyun #define MFTBL(dest) mfspr dest, SPRN_TBRL 84*4882a593Smuzhiyun #define MFTBU(dest) mfspr dest, SPRN_TBRU 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* _PPC64_PPC_ASM_H */ 88