1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MPC8xx support functions
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Scott Wood <scottwood@freescale.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2007 Freescale Semiconductor, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "ops.h"
11*4882a593Smuzhiyun #include "types.h"
12*4882a593Smuzhiyun #include "fsl-soc.h"
13*4882a593Smuzhiyun #include "mpc8xx.h"
14*4882a593Smuzhiyun #include "stdio.h"
15*4882a593Smuzhiyun #include "io.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Return system clock from crystal frequency */
mpc885_get_clock(u32 crystal)20*4882a593Smuzhiyun u32 mpc885_get_clock(u32 crystal)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun u32 *immr;
23*4882a593Smuzhiyun u32 plprcr;
24*4882a593Smuzhiyun int mfi, mfn, mfd, pdf;
25*4882a593Smuzhiyun u32 ret;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun immr = fsl_get_immr();
28*4882a593Smuzhiyun if (!immr) {
29*4882a593Smuzhiyun printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun mfi = (plprcr >> 16) & 15;
36*4882a593Smuzhiyun if (mfi < 5) {
37*4882a593Smuzhiyun printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
38*4882a593Smuzhiyun mfi);
39*4882a593Smuzhiyun mfi = 5;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun pdf = (plprcr >> 1) & 0xf;
43*4882a593Smuzhiyun mfd = (plprcr >> 22) & 0x1f;
44*4882a593Smuzhiyun mfn = (plprcr >> 27) & 0x1f;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = crystal * mfi;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (mfn != 0)
49*4882a593Smuzhiyun ret += crystal * mfn / (mfd + 1);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return ret / (pdf + 1);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Set common device tree fields based on the given clock frequencies. */
mpc8xx_set_clocks(u32 sysclk)55*4882a593Smuzhiyun void mpc8xx_set_clocks(u32 sysclk)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun void *node;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun node = finddevice("/soc/cpm");
62*4882a593Smuzhiyun if (node)
63*4882a593Smuzhiyun setprop(node, "clock-frequency", &sysclk, 4);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun node = finddevice("/soc/cpm/brg");
66*4882a593Smuzhiyun if (node)
67*4882a593Smuzhiyun setprop(node, "clock-frequency", &sysclk, 4);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
mpc885_fixup_clocks(u32 crystal)70*4882a593Smuzhiyun int mpc885_fixup_clocks(u32 crystal)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u32 sysclk = mpc885_get_clock(crystal);
73*4882a593Smuzhiyun if (!sysclk)
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun mpc8xx_set_clocks(sysclk);
77*4882a593Smuzhiyun return 1;
78*4882a593Smuzhiyun }
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