1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/powerpc/boot/gamecube-head.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Nintendo GameCube bootwrapper entry. 6*4882a593Smuzhiyun * Copyright (C) 2004-2009 The GameCube Linux Team 7*4882a593Smuzhiyun * Copyright (C) 2008,2009 Albert Herranz 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "ppc_asm.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/* 13*4882a593Smuzhiyun * The entry code does no assumptions regarding: 14*4882a593Smuzhiyun * - if the data and instruction caches are enabled or not 15*4882a593Smuzhiyun * - if the MMU is enabled or not 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * We enable the caches if not already enabled, enable the MMU with an 18*4882a593Smuzhiyun * identity mapping scheme and jump to the start code. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun .text 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun .globl _zimage_start 24*4882a593Smuzhiyun_zimage_start: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* turn the MMU off */ 27*4882a593Smuzhiyun mfmsr 9 28*4882a593Smuzhiyun rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */ 29*4882a593Smuzhiyun bcl 20, 31, 1f 30*4882a593Smuzhiyun1: 31*4882a593Smuzhiyun mflr 8 32*4882a593Smuzhiyun clrlwi 8, 8, 3 /* convert to a real address */ 33*4882a593Smuzhiyun addi 8, 8, _mmu_off - 1b 34*4882a593Smuzhiyun mtsrr0 8 35*4882a593Smuzhiyun mtsrr1 9 36*4882a593Smuzhiyun rfi 37*4882a593Smuzhiyun_mmu_off: 38*4882a593Smuzhiyun /* MMU disabled */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* setup BATs */ 41*4882a593Smuzhiyun isync 42*4882a593Smuzhiyun li 8, 0 43*4882a593Smuzhiyun mtspr 0x210, 8 /* IBAT0U */ 44*4882a593Smuzhiyun mtspr 0x212, 8 /* IBAT1U */ 45*4882a593Smuzhiyun mtspr 0x214, 8 /* IBAT2U */ 46*4882a593Smuzhiyun mtspr 0x216, 8 /* IBAT3U */ 47*4882a593Smuzhiyun mtspr 0x218, 8 /* DBAT0U */ 48*4882a593Smuzhiyun mtspr 0x21a, 8 /* DBAT1U */ 49*4882a593Smuzhiyun mtspr 0x21c, 8 /* DBAT2U */ 50*4882a593Smuzhiyun mtspr 0x21e, 8 /* DBAT3U */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun li 8, 0x01ff /* first 16MiB */ 53*4882a593Smuzhiyun li 9, 0x0002 /* rw */ 54*4882a593Smuzhiyun mtspr 0x211, 9 /* IBAT0L */ 55*4882a593Smuzhiyun mtspr 0x210, 8 /* IBAT0U */ 56*4882a593Smuzhiyun mtspr 0x219, 9 /* DBAT0L */ 57*4882a593Smuzhiyun mtspr 0x218, 8 /* DBAT0U */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun lis 8, 0x0c00 /* I/O mem */ 60*4882a593Smuzhiyun ori 8, 8, 0x3ff /* 32MiB */ 61*4882a593Smuzhiyun lis 9, 0x0c00 62*4882a593Smuzhiyun ori 9, 9, 0x002a /* uncached, guarded, rw */ 63*4882a593Smuzhiyun mtspr 0x21b, 9 /* DBAT1L */ 64*4882a593Smuzhiyun mtspr 0x21a, 8 /* DBAT1U */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun lis 8, 0x0100 /* next 8MiB */ 67*4882a593Smuzhiyun ori 8, 8, 0x00ff /* 8MiB */ 68*4882a593Smuzhiyun lis 9, 0x0100 69*4882a593Smuzhiyun ori 9, 9, 0x0002 /* rw */ 70*4882a593Smuzhiyun mtspr 0x215, 9 /* IBAT2L */ 71*4882a593Smuzhiyun mtspr 0x214, 8 /* IBAT2U */ 72*4882a593Smuzhiyun mtspr 0x21d, 9 /* DBAT2L */ 73*4882a593Smuzhiyun mtspr 0x21c, 8 /* DBAT2U */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* enable and invalidate the caches if not already enabled */ 76*4882a593Smuzhiyun mfspr 8, 0x3f0 /* HID0 */ 77*4882a593Smuzhiyun andi. 0, 8, (1<<15) /* HID0_ICE */ 78*4882a593Smuzhiyun bne 1f 79*4882a593Smuzhiyun ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/ 80*4882a593Smuzhiyun1: 81*4882a593Smuzhiyun andi. 0, 8, (1<<14) /* HID0_DCE */ 82*4882a593Smuzhiyun bne 1f 83*4882a593Smuzhiyun ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/ 84*4882a593Smuzhiyun1: 85*4882a593Smuzhiyun mtspr 0x3f0, 8 /* HID0 */ 86*4882a593Smuzhiyun isync 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* initialize arguments */ 89*4882a593Smuzhiyun li 3, 0 90*4882a593Smuzhiyun li 4, 0 91*4882a593Smuzhiyun li 5, 0 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* turn the MMU on */ 94*4882a593Smuzhiyun bcl 20, 31, 1f 95*4882a593Smuzhiyun1: 96*4882a593Smuzhiyun mflr 8 97*4882a593Smuzhiyun addi 8, 8, _mmu_on - 1b 98*4882a593Smuzhiyun mfmsr 9 99*4882a593Smuzhiyun ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */ 100*4882a593Smuzhiyun mtsrr0 8 101*4882a593Smuzhiyun mtsrr1 9 102*4882a593Smuzhiyun sync 103*4882a593Smuzhiyun rfi 104*4882a593Smuzhiyun_mmu_on: 105*4882a593Smuzhiyun b _zimage_start_lib 106*4882a593Smuzhiyun 107