1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Manroland uc101 board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 DENX Software Engineering GmbH 6*4882a593Smuzhiyun * Heiko Schocher <hs@denx.de> 7*4882a593Smuzhiyun * Copyright 2006-2007 Secret Lab Technologies Ltd. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "mpc5200b.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun&gpt0 { gpio-controller; }; 13*4882a593Smuzhiyun&gpt1 { gpio-controller; }; 14*4882a593Smuzhiyun&gpt2 { gpio-controller; }; 15*4882a593Smuzhiyun&gpt3 { gpio-controller; }; 16*4882a593Smuzhiyun&gpt4 { gpio-controller; }; 17*4882a593Smuzhiyun&gpt5 { gpio-controller; }; 18*4882a593Smuzhiyun&gpt6 { gpio-controller; }; 19*4882a593Smuzhiyun&gpt7 { gpio-controller; }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/ { 22*4882a593Smuzhiyun model = "manroland,uc101"; 23*4882a593Smuzhiyun compatible = "manroland,uc101"; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun soc5200@f0000000 { 26*4882a593Smuzhiyun rtc@800 { 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun can@900 { 31*4882a593Smuzhiyun status = "disabled"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun can@980 { 35*4882a593Smuzhiyun status = "disabled"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun spi@f00 { 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun usb@1000 { 43*4882a593Smuzhiyun status = "disabled"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun psc@2000 { // PSC1 47*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun psc@2200 { // PSC2 51*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun psc@2400 { // PSC3 55*4882a593Smuzhiyun status = "disabled"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun psc@2600 { // PSC4 59*4882a593Smuzhiyun status = "disabled"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun psc@2800 { // PSC5 63*4882a593Smuzhiyun status = "disabled"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun psc@2c00 { // PSC6 67*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun ethernet@3000 { 71*4882a593Smuzhiyun phy-handle = <&phy0>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun mdio@3000 { 75*4882a593Smuzhiyun phy0: ethernet-phy@0 { 76*4882a593Smuzhiyun compatible = "intel,lxt971"; 77*4882a593Smuzhiyun reg = <0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun i2c@3d00 { 82*4882a593Smuzhiyun status = "disabled"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun i2c@3d40 { 86*4882a593Smuzhiyun fsl,preserve-clocking; 87*4882a593Smuzhiyun clock-frequency = <400000>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun hwmon@2c { 90*4882a593Smuzhiyun compatible = "ad,adm9240"; 91*4882a593Smuzhiyun reg = <0x2c>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun rtc@51 { 94*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 95*4882a593Smuzhiyun reg = <0x51>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pci@f0000d00 { 101*4882a593Smuzhiyun status = "disabled"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun localbus { 105*4882a593Smuzhiyun ranges = <0 0 0xff800000 0x00800000 106*4882a593Smuzhiyun 1 0 0x80000000 0x00800000 107*4882a593Smuzhiyun 3 0 0x80000000 0x00800000>; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun flash@0,0 { 110*4882a593Smuzhiyun compatible = "cfi-flash"; 111*4882a593Smuzhiyun reg = <0 0 0x00800000>; 112*4882a593Smuzhiyun bank-width = <2>; 113*4882a593Smuzhiyun device-width = <2>; 114*4882a593Smuzhiyun #size-cells = <1>; 115*4882a593Smuzhiyun #address-cells = <1>; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun partition@0 { 118*4882a593Smuzhiyun label = "DTS"; 119*4882a593Smuzhiyun reg = <0x0 0x00100000>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun partition@100000 { 122*4882a593Smuzhiyun label = "Kernel"; 123*4882a593Smuzhiyun reg = <0x100000 0x00200000>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun partition@300000 { 126*4882a593Smuzhiyun label = "RootFS"; 127*4882a593Smuzhiyun reg = <0x00300000 0x00200000>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun partition@500000 { 130*4882a593Smuzhiyun label = "user"; 131*4882a593Smuzhiyun reg = <0x00500000 0x00200000>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun partition@700000 { 134*4882a593Smuzhiyun label = "U-Boot"; 135*4882a593Smuzhiyun reg = <0x00700000 0x00040000>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun partition@740000 { 138*4882a593Smuzhiyun label = "Env"; 139*4882a593Smuzhiyun reg = <0x00740000 0x00010000>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun partition@750000 { 142*4882a593Smuzhiyun label = "red. Env"; 143*4882a593Smuzhiyun reg = <0x00750000 0x00010000>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun partition@760000 { 146*4882a593Smuzhiyun label = "reserve"; 147*4882a593Smuzhiyun reg = <0x00760000 0x000a0000>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun}; 153