1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * TQM 8560 Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "tqc,tqm8560"; 13*4882a593Smuzhiyun compatible = "tqc,tqm8560"; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun ethernet0 = &enet0; 19*4882a593Smuzhiyun ethernet1 = &enet1; 20*4882a593Smuzhiyun ethernet2 = &enet2; 21*4882a593Smuzhiyun serial0 = &serial0; 22*4882a593Smuzhiyun serial1 = &serial1; 23*4882a593Smuzhiyun pci0 = &pci0; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpus { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun PowerPC,8560@0 { 31*4882a593Smuzhiyun device_type = "cpu"; 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun d-cache-line-size = <32>; 34*4882a593Smuzhiyun i-cache-line-size = <32>; 35*4882a593Smuzhiyun d-cache-size = <32768>; 36*4882a593Smuzhiyun i-cache-size = <32768>; 37*4882a593Smuzhiyun timebase-frequency = <0>; 38*4882a593Smuzhiyun bus-frequency = <0>; 39*4882a593Smuzhiyun clock-frequency = <0>; 40*4882a593Smuzhiyun next-level-cache = <&L2>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun memory { 45*4882a593Smuzhiyun device_type = "memory"; 46*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun soc@e0000000 { 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <1>; 52*4882a593Smuzhiyun device_type = "soc"; 53*4882a593Smuzhiyun ranges = <0x0 0xe0000000 0x100000>; 54*4882a593Smuzhiyun bus-frequency = <0>; 55*4882a593Smuzhiyun compatible = "fsl,mpc8560-immr", "simple-bus"; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun ecm-law@0 { 58*4882a593Smuzhiyun compatible = "fsl,ecm-law"; 59*4882a593Smuzhiyun reg = <0x0 0x1000>; 60*4882a593Smuzhiyun fsl,num-laws = <8>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun ecm@1000 { 64*4882a593Smuzhiyun compatible = "fsl,mpc8560-ecm", "fsl,ecm"; 65*4882a593Smuzhiyun reg = <0x1000 0x1000>; 66*4882a593Smuzhiyun interrupts = <17 2>; 67*4882a593Smuzhiyun interrupt-parent = <&mpic>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun memory-controller@2000 { 71*4882a593Smuzhiyun compatible = "fsl,mpc8540-memory-controller"; 72*4882a593Smuzhiyun reg = <0x2000 0x1000>; 73*4882a593Smuzhiyun interrupt-parent = <&mpic>; 74*4882a593Smuzhiyun interrupts = <18 2>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun L2: l2-cache-controller@20000 { 78*4882a593Smuzhiyun compatible = "fsl,mpc8540-l2-cache-controller"; 79*4882a593Smuzhiyun reg = <0x20000 0x1000>; 80*4882a593Smuzhiyun cache-line-size = <32>; 81*4882a593Smuzhiyun cache-size = <0x40000>; // L2, 256K 82*4882a593Smuzhiyun interrupt-parent = <&mpic>; 83*4882a593Smuzhiyun interrupts = <16 2>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun i2c@3000 { 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun cell-index = <0>; 90*4882a593Smuzhiyun compatible = "fsl-i2c"; 91*4882a593Smuzhiyun reg = <0x3000 0x100>; 92*4882a593Smuzhiyun interrupts = <43 2>; 93*4882a593Smuzhiyun interrupt-parent = <&mpic>; 94*4882a593Smuzhiyun dfsrr; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun dtt@48 { 97*4882a593Smuzhiyun compatible = "national,lm75"; 98*4882a593Smuzhiyun reg = <0x48>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun rtc@68 { 102*4882a593Smuzhiyun compatible = "dallas,ds1337"; 103*4882a593Smuzhiyun reg = <0x68>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun dma@21300 { 108*4882a593Smuzhiyun #address-cells = <1>; 109*4882a593Smuzhiyun #size-cells = <1>; 110*4882a593Smuzhiyun compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma"; 111*4882a593Smuzhiyun reg = <0x21300 0x4>; 112*4882a593Smuzhiyun ranges = <0x0 0x21100 0x200>; 113*4882a593Smuzhiyun cell-index = <0>; 114*4882a593Smuzhiyun dma-channel@0 { 115*4882a593Smuzhiyun compatible = "fsl,mpc8560-dma-channel", 116*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 117*4882a593Smuzhiyun reg = <0x0 0x80>; 118*4882a593Smuzhiyun cell-index = <0>; 119*4882a593Smuzhiyun interrupt-parent = <&mpic>; 120*4882a593Smuzhiyun interrupts = <20 2>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun dma-channel@80 { 123*4882a593Smuzhiyun compatible = "fsl,mpc8560-dma-channel", 124*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 125*4882a593Smuzhiyun reg = <0x80 0x80>; 126*4882a593Smuzhiyun cell-index = <1>; 127*4882a593Smuzhiyun interrupt-parent = <&mpic>; 128*4882a593Smuzhiyun interrupts = <21 2>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun dma-channel@100 { 131*4882a593Smuzhiyun compatible = "fsl,mpc8560-dma-channel", 132*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 133*4882a593Smuzhiyun reg = <0x100 0x80>; 134*4882a593Smuzhiyun cell-index = <2>; 135*4882a593Smuzhiyun interrupt-parent = <&mpic>; 136*4882a593Smuzhiyun interrupts = <22 2>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun dma-channel@180 { 139*4882a593Smuzhiyun compatible = "fsl,mpc8560-dma-channel", 140*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 141*4882a593Smuzhiyun reg = <0x180 0x80>; 142*4882a593Smuzhiyun cell-index = <3>; 143*4882a593Smuzhiyun interrupt-parent = <&mpic>; 144*4882a593Smuzhiyun interrupts = <23 2>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun enet0: ethernet@24000 { 149*4882a593Smuzhiyun #address-cells = <1>; 150*4882a593Smuzhiyun #size-cells = <1>; 151*4882a593Smuzhiyun cell-index = <0>; 152*4882a593Smuzhiyun device_type = "network"; 153*4882a593Smuzhiyun model = "TSEC"; 154*4882a593Smuzhiyun compatible = "gianfar"; 155*4882a593Smuzhiyun reg = <0x24000 0x1000>; 156*4882a593Smuzhiyun ranges = <0x0 0x24000 0x1000>; 157*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 158*4882a593Smuzhiyun interrupts = <29 2 30 2 34 2>; 159*4882a593Smuzhiyun interrupt-parent = <&mpic>; 160*4882a593Smuzhiyun tbi-handle = <&tbi0>; 161*4882a593Smuzhiyun phy-handle = <&phy2>; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun mdio@520 { 164*4882a593Smuzhiyun #address-cells = <1>; 165*4882a593Smuzhiyun #size-cells = <0>; 166*4882a593Smuzhiyun compatible = "fsl,gianfar-mdio"; 167*4882a593Smuzhiyun reg = <0x520 0x20>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun phy1: ethernet-phy@1 { 170*4882a593Smuzhiyun interrupt-parent = <&mpic>; 171*4882a593Smuzhiyun interrupts = <8 1>; 172*4882a593Smuzhiyun reg = <1>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun phy2: ethernet-phy@2 { 175*4882a593Smuzhiyun interrupt-parent = <&mpic>; 176*4882a593Smuzhiyun interrupts = <8 1>; 177*4882a593Smuzhiyun reg = <2>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun phy3: ethernet-phy@3 { 180*4882a593Smuzhiyun interrupt-parent = <&mpic>; 181*4882a593Smuzhiyun interrupts = <8 1>; 182*4882a593Smuzhiyun reg = <3>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun tbi0: tbi-phy@11 { 185*4882a593Smuzhiyun reg = <0x11>; 186*4882a593Smuzhiyun device_type = "tbi-phy"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun enet1: ethernet@25000 { 192*4882a593Smuzhiyun #address-cells = <1>; 193*4882a593Smuzhiyun #size-cells = <1>; 194*4882a593Smuzhiyun cell-index = <1>; 195*4882a593Smuzhiyun device_type = "network"; 196*4882a593Smuzhiyun model = "TSEC"; 197*4882a593Smuzhiyun compatible = "gianfar"; 198*4882a593Smuzhiyun reg = <0x25000 0x1000>; 199*4882a593Smuzhiyun ranges = <0x0 0x25000 0x1000>; 200*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 201*4882a593Smuzhiyun interrupts = <35 2 36 2 40 2>; 202*4882a593Smuzhiyun interrupt-parent = <&mpic>; 203*4882a593Smuzhiyun tbi-handle = <&tbi1>; 204*4882a593Smuzhiyun phy-handle = <&phy1>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun mdio@520 { 207*4882a593Smuzhiyun #address-cells = <1>; 208*4882a593Smuzhiyun #size-cells = <0>; 209*4882a593Smuzhiyun compatible = "fsl,gianfar-tbi"; 210*4882a593Smuzhiyun reg = <0x520 0x20>; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun tbi1: tbi-phy@11 { 213*4882a593Smuzhiyun reg = <0x11>; 214*4882a593Smuzhiyun device_type = "tbi-phy"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun mpic: pic@40000 { 220*4882a593Smuzhiyun interrupt-controller; 221*4882a593Smuzhiyun #address-cells = <0>; 222*4882a593Smuzhiyun #interrupt-cells = <2>; 223*4882a593Smuzhiyun reg = <0x40000 0x40000>; 224*4882a593Smuzhiyun device_type = "open-pic"; 225*4882a593Smuzhiyun compatible = "chrp,open-pic"; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun cpm@919c0 { 229*4882a593Smuzhiyun #address-cells = <1>; 230*4882a593Smuzhiyun #size-cells = <1>; 231*4882a593Smuzhiyun compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus"; 232*4882a593Smuzhiyun reg = <0x919c0 0x30>; 233*4882a593Smuzhiyun ranges; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun muram@80000 { 236*4882a593Smuzhiyun #address-cells = <1>; 237*4882a593Smuzhiyun #size-cells = <1>; 238*4882a593Smuzhiyun ranges = <0 0x80000 0x10000>; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun data@0 { 241*4882a593Smuzhiyun compatible = "fsl,cpm-muram-data"; 242*4882a593Smuzhiyun reg = <0 0x4000 0x9000 0x2000>; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun brg@919f0 { 247*4882a593Smuzhiyun compatible = "fsl,mpc8560-brg", 248*4882a593Smuzhiyun "fsl,cpm2-brg", 249*4882a593Smuzhiyun "fsl,cpm-brg"; 250*4882a593Smuzhiyun reg = <0x919f0 0x10 0x915f0 0x10>; 251*4882a593Smuzhiyun clock-frequency = <0>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun cpmpic: pic@90c00 { 255*4882a593Smuzhiyun interrupt-controller; 256*4882a593Smuzhiyun #address-cells = <0>; 257*4882a593Smuzhiyun #interrupt-cells = <2>; 258*4882a593Smuzhiyun interrupts = <46 2>; 259*4882a593Smuzhiyun interrupt-parent = <&mpic>; 260*4882a593Smuzhiyun reg = <0x90c00 0x80>; 261*4882a593Smuzhiyun compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic"; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun serial0: serial@91a00 { 265*4882a593Smuzhiyun device_type = "serial"; 266*4882a593Smuzhiyun compatible = "fsl,mpc8560-scc-uart", 267*4882a593Smuzhiyun "fsl,cpm2-scc-uart"; 268*4882a593Smuzhiyun reg = <0x91a00 0x20 0x88000 0x100>; 269*4882a593Smuzhiyun fsl,cpm-brg = <1>; 270*4882a593Smuzhiyun fsl,cpm-command = <0x800000>; 271*4882a593Smuzhiyun current-speed = <115200>; 272*4882a593Smuzhiyun interrupts = <40 8>; 273*4882a593Smuzhiyun interrupt-parent = <&cpmpic>; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun serial1: serial@91a20 { 277*4882a593Smuzhiyun device_type = "serial"; 278*4882a593Smuzhiyun compatible = "fsl,mpc8560-scc-uart", 279*4882a593Smuzhiyun "fsl,cpm2-scc-uart"; 280*4882a593Smuzhiyun reg = <0x91a20 0x20 0x88100 0x100>; 281*4882a593Smuzhiyun fsl,cpm-brg = <2>; 282*4882a593Smuzhiyun fsl,cpm-command = <0x4a00000>; 283*4882a593Smuzhiyun current-speed = <115200>; 284*4882a593Smuzhiyun interrupts = <41 8>; 285*4882a593Smuzhiyun interrupt-parent = <&cpmpic>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun enet2: ethernet@91340 { 289*4882a593Smuzhiyun device_type = "network"; 290*4882a593Smuzhiyun compatible = "fsl,mpc8560-fcc-enet", 291*4882a593Smuzhiyun "fsl,cpm2-fcc-enet"; 292*4882a593Smuzhiyun reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>; 293*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 294*4882a593Smuzhiyun fsl,cpm-command = <0x1a400300>; 295*4882a593Smuzhiyun interrupts = <34 8>; 296*4882a593Smuzhiyun interrupt-parent = <&cpmpic>; 297*4882a593Smuzhiyun phy-handle = <&phy3>; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun localbus@e0005000 { 303*4882a593Smuzhiyun compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus", 304*4882a593Smuzhiyun "simple-bus"; 305*4882a593Smuzhiyun #address-cells = <2>; 306*4882a593Smuzhiyun #size-cells = <1>; 307*4882a593Smuzhiyun reg = <0xe0005000 0x100>; // BRx, ORx, etc. 308*4882a593Smuzhiyun interrupt-parent = <&mpic>; 309*4882a593Smuzhiyun interrupts = <19 2>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun ranges = < 312*4882a593Smuzhiyun 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 313*4882a593Smuzhiyun 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 314*4882a593Smuzhiyun 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) 315*4882a593Smuzhiyun >; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun flash@1,0 { 318*4882a593Smuzhiyun #address-cells = <1>; 319*4882a593Smuzhiyun #size-cells = <1>; 320*4882a593Smuzhiyun compatible = "cfi-flash"; 321*4882a593Smuzhiyun reg = <1 0x0 0x8000000>; 322*4882a593Smuzhiyun bank-width = <4>; 323*4882a593Smuzhiyun device-width = <1>; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun partition@0 { 326*4882a593Smuzhiyun label = "kernel"; 327*4882a593Smuzhiyun reg = <0x00000000 0x00200000>; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun partition@200000 { 330*4882a593Smuzhiyun label = "root"; 331*4882a593Smuzhiyun reg = <0x00200000 0x00300000>; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun partition@500000 { 334*4882a593Smuzhiyun label = "user"; 335*4882a593Smuzhiyun reg = <0x00500000 0x07a00000>; 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun partition@7f00000 { 338*4882a593Smuzhiyun label = "env1"; 339*4882a593Smuzhiyun reg = <0x07f00000 0x00040000>; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun partition@7f40000 { 342*4882a593Smuzhiyun label = "env2"; 343*4882a593Smuzhiyun reg = <0x07f40000 0x00040000>; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun partition@7f80000 { 346*4882a593Smuzhiyun label = "u-boot"; 347*4882a593Smuzhiyun reg = <0x07f80000 0x00080000>; 348*4882a593Smuzhiyun read-only; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* Note: CAN support needs be enabled in U-Boot */ 353*4882a593Smuzhiyun can0@2,0 { 354*4882a593Smuzhiyun compatible = "intel,82527"; // Bosch CC770 355*4882a593Smuzhiyun reg = <2 0x0 0x100>; 356*4882a593Smuzhiyun interrupts = <4 1>; 357*4882a593Smuzhiyun interrupt-parent = <&mpic>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun can1@2,100 { 361*4882a593Smuzhiyun compatible = "intel,82527"; // Bosch CC770 362*4882a593Smuzhiyun reg = <2 0x100 0x100>; 363*4882a593Smuzhiyun interrupts = <4 1>; 364*4882a593Smuzhiyun interrupt-parent = <&mpic>; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pci0: pci@e0008000 { 369*4882a593Smuzhiyun #interrupt-cells = <1>; 370*4882a593Smuzhiyun #size-cells = <2>; 371*4882a593Smuzhiyun #address-cells = <3>; 372*4882a593Smuzhiyun compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 373*4882a593Smuzhiyun device_type = "pci"; 374*4882a593Smuzhiyun reg = <0xe0008000 0x1000>; 375*4882a593Smuzhiyun clock-frequency = <66666666>; 376*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 377*4882a593Smuzhiyun interrupt-map = < 378*4882a593Smuzhiyun /* IDSEL 28 */ 379*4882a593Smuzhiyun 0xe000 0 0 1 &mpic 2 1 380*4882a593Smuzhiyun 0xe000 0 0 2 &mpic 3 1 381*4882a593Smuzhiyun 0xe000 0 0 3 &mpic 6 1 382*4882a593Smuzhiyun 0xe000 0 0 4 &mpic 5 1 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* IDSEL 11 */ 385*4882a593Smuzhiyun 0x5800 0 0 1 &mpic 6 1 386*4882a593Smuzhiyun 0x5800 0 0 2 &mpic 5 1 387*4882a593Smuzhiyun >; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun interrupt-parent = <&mpic>; 390*4882a593Smuzhiyun interrupts = <24 2>; 391*4882a593Smuzhiyun bus-range = <0 0>; 392*4882a593Smuzhiyun ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 393*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun}; 396