1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * TQM 8540 Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "tqc,tqm8540"; 12*4882a593Smuzhiyun compatible = "tqc,tqm8540"; 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun ethernet0 = &enet0; 18*4882a593Smuzhiyun ethernet1 = &enet1; 19*4882a593Smuzhiyun ethernet2 = &enet2; 20*4882a593Smuzhiyun serial0 = &serial0; 21*4882a593Smuzhiyun serial1 = &serial1; 22*4882a593Smuzhiyun pci0 = &pci0; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpus { 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun PowerPC,8540@0 { 30*4882a593Smuzhiyun device_type = "cpu"; 31*4882a593Smuzhiyun reg = <0>; 32*4882a593Smuzhiyun d-cache-line-size = <32>; 33*4882a593Smuzhiyun i-cache-line-size = <32>; 34*4882a593Smuzhiyun d-cache-size = <32768>; 35*4882a593Smuzhiyun i-cache-size = <32768>; 36*4882a593Smuzhiyun timebase-frequency = <0>; 37*4882a593Smuzhiyun bus-frequency = <0>; 38*4882a593Smuzhiyun clock-frequency = <0>; 39*4882a593Smuzhiyun next-level-cache = <&L2>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun memory { 44*4882a593Smuzhiyun device_type = "memory"; 45*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun soc@e0000000 { 49*4882a593Smuzhiyun #address-cells = <1>; 50*4882a593Smuzhiyun #size-cells = <1>; 51*4882a593Smuzhiyun device_type = "soc"; 52*4882a593Smuzhiyun ranges = <0x0 0xe0000000 0x100000>; 53*4882a593Smuzhiyun bus-frequency = <0>; 54*4882a593Smuzhiyun compatible = "fsl,mpc8540-immr", "simple-bus"; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ecm-law@0 { 57*4882a593Smuzhiyun compatible = "fsl,ecm-law"; 58*4882a593Smuzhiyun reg = <0x0 0x1000>; 59*4882a593Smuzhiyun fsl,num-laws = <8>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun ecm@1000 { 63*4882a593Smuzhiyun compatible = "fsl,mpc8540-ecm", "fsl,ecm"; 64*4882a593Smuzhiyun reg = <0x1000 0x1000>; 65*4882a593Smuzhiyun interrupts = <17 2>; 66*4882a593Smuzhiyun interrupt-parent = <&mpic>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun memory-controller@2000 { 70*4882a593Smuzhiyun compatible = "fsl,mpc8540-memory-controller"; 71*4882a593Smuzhiyun reg = <0x2000 0x1000>; 72*4882a593Smuzhiyun interrupt-parent = <&mpic>; 73*4882a593Smuzhiyun interrupts = <18 2>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun L2: l2-cache-controller@20000 { 77*4882a593Smuzhiyun compatible = "fsl,mpc8540-l2-cache-controller"; 78*4882a593Smuzhiyun reg = <0x20000 0x1000>; 79*4882a593Smuzhiyun cache-line-size = <32>; 80*4882a593Smuzhiyun cache-size = <0x40000>; // L2, 256K 81*4882a593Smuzhiyun interrupt-parent = <&mpic>; 82*4882a593Smuzhiyun interrupts = <16 2>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun i2c@3000 { 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun cell-index = <0>; 89*4882a593Smuzhiyun compatible = "fsl-i2c"; 90*4882a593Smuzhiyun reg = <0x3000 0x100>; 91*4882a593Smuzhiyun interrupts = <43 2>; 92*4882a593Smuzhiyun interrupt-parent = <&mpic>; 93*4882a593Smuzhiyun dfsrr; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun dtt@48 { 96*4882a593Smuzhiyun compatible = "national,lm75"; 97*4882a593Smuzhiyun reg = <0x48>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun rtc@68 { 101*4882a593Smuzhiyun compatible = "dallas,ds1337"; 102*4882a593Smuzhiyun reg = <0x68>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun dma@21300 { 107*4882a593Smuzhiyun #address-cells = <1>; 108*4882a593Smuzhiyun #size-cells = <1>; 109*4882a593Smuzhiyun compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 110*4882a593Smuzhiyun reg = <0x21300 0x4>; 111*4882a593Smuzhiyun ranges = <0x0 0x21100 0x200>; 112*4882a593Smuzhiyun cell-index = <0>; 113*4882a593Smuzhiyun dma-channel@0 { 114*4882a593Smuzhiyun compatible = "fsl,mpc8540-dma-channel", 115*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 116*4882a593Smuzhiyun reg = <0x0 0x80>; 117*4882a593Smuzhiyun cell-index = <0>; 118*4882a593Smuzhiyun interrupt-parent = <&mpic>; 119*4882a593Smuzhiyun interrupts = <20 2>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun dma-channel@80 { 122*4882a593Smuzhiyun compatible = "fsl,mpc8540-dma-channel", 123*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 124*4882a593Smuzhiyun reg = <0x80 0x80>; 125*4882a593Smuzhiyun cell-index = <1>; 126*4882a593Smuzhiyun interrupt-parent = <&mpic>; 127*4882a593Smuzhiyun interrupts = <21 2>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun dma-channel@100 { 130*4882a593Smuzhiyun compatible = "fsl,mpc8540-dma-channel", 131*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 132*4882a593Smuzhiyun reg = <0x100 0x80>; 133*4882a593Smuzhiyun cell-index = <2>; 134*4882a593Smuzhiyun interrupt-parent = <&mpic>; 135*4882a593Smuzhiyun interrupts = <22 2>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun dma-channel@180 { 138*4882a593Smuzhiyun compatible = "fsl,mpc8540-dma-channel", 139*4882a593Smuzhiyun "fsl,eloplus-dma-channel"; 140*4882a593Smuzhiyun reg = <0x180 0x80>; 141*4882a593Smuzhiyun cell-index = <3>; 142*4882a593Smuzhiyun interrupt-parent = <&mpic>; 143*4882a593Smuzhiyun interrupts = <23 2>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun enet0: ethernet@24000 { 148*4882a593Smuzhiyun #address-cells = <1>; 149*4882a593Smuzhiyun #size-cells = <1>; 150*4882a593Smuzhiyun cell-index = <0>; 151*4882a593Smuzhiyun device_type = "network"; 152*4882a593Smuzhiyun model = "TSEC"; 153*4882a593Smuzhiyun compatible = "gianfar"; 154*4882a593Smuzhiyun reg = <0x24000 0x1000>; 155*4882a593Smuzhiyun ranges = <0x0 0x24000 0x1000>; 156*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 157*4882a593Smuzhiyun interrupts = <29 2 30 2 34 2>; 158*4882a593Smuzhiyun interrupt-parent = <&mpic>; 159*4882a593Smuzhiyun phy-handle = <&phy2>; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun mdio@520 { 162*4882a593Smuzhiyun #address-cells = <1>; 163*4882a593Smuzhiyun #size-cells = <0>; 164*4882a593Smuzhiyun compatible = "fsl,gianfar-mdio"; 165*4882a593Smuzhiyun reg = <0x520 0x20>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun phy1: ethernet-phy@1 { 168*4882a593Smuzhiyun interrupt-parent = <&mpic>; 169*4882a593Smuzhiyun interrupts = <8 1>; 170*4882a593Smuzhiyun reg = <1>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun phy2: ethernet-phy@2 { 173*4882a593Smuzhiyun interrupt-parent = <&mpic>; 174*4882a593Smuzhiyun interrupts = <8 1>; 175*4882a593Smuzhiyun reg = <2>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun phy3: ethernet-phy@3 { 178*4882a593Smuzhiyun interrupt-parent = <&mpic>; 179*4882a593Smuzhiyun interrupts = <8 1>; 180*4882a593Smuzhiyun reg = <3>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun tbi0: tbi-phy@11 { 183*4882a593Smuzhiyun reg = <0x11>; 184*4882a593Smuzhiyun device_type = "tbi-phy"; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun enet1: ethernet@25000 { 190*4882a593Smuzhiyun #address-cells = <1>; 191*4882a593Smuzhiyun #size-cells = <1>; 192*4882a593Smuzhiyun cell-index = <1>; 193*4882a593Smuzhiyun device_type = "network"; 194*4882a593Smuzhiyun model = "TSEC"; 195*4882a593Smuzhiyun compatible = "gianfar"; 196*4882a593Smuzhiyun reg = <0x25000 0x1000>; 197*4882a593Smuzhiyun ranges = <0x0 0x25000 0x1000>; 198*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 199*4882a593Smuzhiyun interrupts = <35 2 36 2 40 2>; 200*4882a593Smuzhiyun interrupt-parent = <&mpic>; 201*4882a593Smuzhiyun phy-handle = <&phy1>; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun mdio@520 { 204*4882a593Smuzhiyun #address-cells = <1>; 205*4882a593Smuzhiyun #size-cells = <0>; 206*4882a593Smuzhiyun compatible = "fsl,gianfar-tbi"; 207*4882a593Smuzhiyun reg = <0x520 0x20>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun tbi1: tbi-phy@11 { 210*4882a593Smuzhiyun reg = <0x11>; 211*4882a593Smuzhiyun device_type = "tbi-phy"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun enet2: ethernet@26000 { 217*4882a593Smuzhiyun #address-cells = <1>; 218*4882a593Smuzhiyun #size-cells = <1>; 219*4882a593Smuzhiyun cell-index = <2>; 220*4882a593Smuzhiyun device_type = "network"; 221*4882a593Smuzhiyun model = "FEC"; 222*4882a593Smuzhiyun compatible = "gianfar"; 223*4882a593Smuzhiyun reg = <0x26000 0x1000>; 224*4882a593Smuzhiyun ranges = <0x0 0x26000 0x1000>; 225*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 226*4882a593Smuzhiyun interrupts = <41 2>; 227*4882a593Smuzhiyun interrupt-parent = <&mpic>; 228*4882a593Smuzhiyun phy-handle = <&phy3>; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun mdio@520 { 231*4882a593Smuzhiyun #address-cells = <1>; 232*4882a593Smuzhiyun #size-cells = <0>; 233*4882a593Smuzhiyun compatible = "fsl,gianfar-tbi"; 234*4882a593Smuzhiyun reg = <0x520 0x20>; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun tbi2: tbi-phy@11 { 237*4882a593Smuzhiyun reg = <0x11>; 238*4882a593Smuzhiyun device_type = "tbi-phy"; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun serial0: serial@4500 { 244*4882a593Smuzhiyun cell-index = <0>; 245*4882a593Smuzhiyun device_type = "serial"; 246*4882a593Smuzhiyun compatible = "fsl,ns16550", "ns16550"; 247*4882a593Smuzhiyun reg = <0x4500 0x100>; // reg base, size 248*4882a593Smuzhiyun clock-frequency = <0>; // should we fill in in uboot? 249*4882a593Smuzhiyun interrupts = <42 2>; 250*4882a593Smuzhiyun interrupt-parent = <&mpic>; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun serial1: serial@4600 { 254*4882a593Smuzhiyun cell-index = <1>; 255*4882a593Smuzhiyun device_type = "serial"; 256*4882a593Smuzhiyun compatible = "fsl,ns16550", "ns16550"; 257*4882a593Smuzhiyun reg = <0x4600 0x100>; // reg base, size 258*4882a593Smuzhiyun clock-frequency = <0>; // should we fill in in uboot? 259*4882a593Smuzhiyun interrupts = <42 2>; 260*4882a593Smuzhiyun interrupt-parent = <&mpic>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun mpic: pic@40000 { 264*4882a593Smuzhiyun interrupt-controller; 265*4882a593Smuzhiyun #address-cells = <0>; 266*4882a593Smuzhiyun #interrupt-cells = <2>; 267*4882a593Smuzhiyun reg = <0x40000 0x40000>; 268*4882a593Smuzhiyun device_type = "open-pic"; 269*4882a593Smuzhiyun compatible = "chrp,open-pic"; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun localbus@e0005000 { 274*4882a593Smuzhiyun #address-cells = <2>; 275*4882a593Smuzhiyun #size-cells = <1>; 276*4882a593Smuzhiyun compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus", 277*4882a593Smuzhiyun "simple-bus"; 278*4882a593Smuzhiyun reg = <0xe0005000 0x1000>; 279*4882a593Smuzhiyun interrupt-parent = <&mpic>; 280*4882a593Smuzhiyun interrupts = <19 2>; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun ranges = <0x0 0x0 0xfe000000 0x02000000>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun nor@0,0 { 285*4882a593Smuzhiyun #address-cells = <1>; 286*4882a593Smuzhiyun #size-cells = <1>; 287*4882a593Smuzhiyun compatible = "cfi-flash"; 288*4882a593Smuzhiyun reg = <0x0 0x0 0x02000000>; 289*4882a593Smuzhiyun bank-width = <4>; 290*4882a593Smuzhiyun device-width = <2>; 291*4882a593Smuzhiyun partition@0 { 292*4882a593Smuzhiyun label = "kernel"; 293*4882a593Smuzhiyun reg = <0x00000000 0x00180000>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun partition@180000 { 296*4882a593Smuzhiyun label = "root"; 297*4882a593Smuzhiyun reg = <0x00180000 0x01dc0000>; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun partition@1f40000 { 300*4882a593Smuzhiyun label = "env1"; 301*4882a593Smuzhiyun reg = <0x01f40000 0x00040000>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun partition@1f80000 { 304*4882a593Smuzhiyun label = "env2"; 305*4882a593Smuzhiyun reg = <0x01f80000 0x00040000>; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun partition@1fc0000 { 308*4882a593Smuzhiyun label = "u-boot"; 309*4882a593Smuzhiyun reg = <0x01fc0000 0x00040000>; 310*4882a593Smuzhiyun read-only; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun pci0: pci@e0008000 { 316*4882a593Smuzhiyun #interrupt-cells = <1>; 317*4882a593Smuzhiyun #size-cells = <2>; 318*4882a593Smuzhiyun #address-cells = <3>; 319*4882a593Smuzhiyun compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 320*4882a593Smuzhiyun device_type = "pci"; 321*4882a593Smuzhiyun reg = <0xe0008000 0x1000>; 322*4882a593Smuzhiyun clock-frequency = <66666666>; 323*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 324*4882a593Smuzhiyun interrupt-map = < 325*4882a593Smuzhiyun /* IDSEL 28 */ 326*4882a593Smuzhiyun 0xe000 0 0 1 &mpic 2 1 327*4882a593Smuzhiyun 0xe000 0 0 2 &mpic 3 1 328*4882a593Smuzhiyun 0xe000 0 0 3 &mpic 6 1 329*4882a593Smuzhiyun 0xe000 0 0 4 &mpic 5 1 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* IDSEL 11 */ 332*4882a593Smuzhiyun 0x5800 0 0 1 &mpic 6 1 333*4882a593Smuzhiyun 0x5800 0 0 2 &mpic 5 1 334*4882a593Smuzhiyun >; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun interrupt-parent = <&mpic>; 337*4882a593Smuzhiyun interrupts = <24 2>; 338*4882a593Smuzhiyun bus-range = <0 0>; 339*4882a593Smuzhiyun ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 340*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun}; 343