1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * PS3 Game Console device tree. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Sony Computer Entertainment Inc. 6*4882a593Smuzhiyun * Copyright 2007 Sony Corp. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "SonyPS3"; 13*4882a593Smuzhiyun compatible = "sony,ps3"; 14*4882a593Smuzhiyun #size-cells = <2>; 15*4882a593Smuzhiyun #address-cells = <2>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * We'll get the size of the bootmem block from lv1 after startup, 22*4882a593Smuzhiyun * so we'll put a null entry here. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun memory { 26*4882a593Smuzhiyun device_type = "memory"; 27*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x00000000 0x00000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * The boot cpu is always zero for PS3. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * dtc expects a clock-frequency and timebase-frequency entries, so 34*4882a593Smuzhiyun * we'll put a null entries here. These will be initialized after 35*4882a593Smuzhiyun * startup with data from lv1. 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * Seems the only way currently to indicate a processor has multiple 38*4882a593Smuzhiyun * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one 39*4882a593Smuzhiyun * here so we can bring up both of ours. See smp_setup_cpu_maps(). 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cpus { 43*4882a593Smuzhiyun #size-cells = <0>; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun cpu@0 { 47*4882a593Smuzhiyun device_type = "cpu"; 48*4882a593Smuzhiyun reg = <0x00000000>; 49*4882a593Smuzhiyun ibm,ppc-interrupt-server#s = <0x0 0x1>; 50*4882a593Smuzhiyun clock-frequency = <0>; 51*4882a593Smuzhiyun timebase-frequency = <0>; 52*4882a593Smuzhiyun i-cache-size = <32768>; 53*4882a593Smuzhiyun d-cache-size = <32768>; 54*4882a593Smuzhiyun i-cache-line-size = <128>; 55*4882a593Smuzhiyun d-cache-line-size = <128>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun}; 59