1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for IFM PDM360NG. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 - 2010 DENX Software Engineering. 6*4882a593Smuzhiyun * Anatolij Gustschin <agust@denx.de> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on MPC5121E ADS dts. 9*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor Inc. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "mpc5121.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "pdm360ng"; 16*4882a593Smuzhiyun compatible = "ifm,pdm360ng", "fsl,mpc5121"; 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <1>; 19*4882a593Smuzhiyun interrupt-parent = <&ipic>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; // 512MB at 0 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun nfc@40000000 { 27*4882a593Smuzhiyun bank-width = <0x1>; 28*4882a593Smuzhiyun chips = <0x1>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun partition@0 { 31*4882a593Smuzhiyun label = "nand0"; 32*4882a593Smuzhiyun reg = <0x0 0x40000000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun localbus@80000020 { 37*4882a593Smuzhiyun ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */ 38*4882a593Smuzhiyun 0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun flash@0,0 { 41*4882a593Smuzhiyun compatible = "amd,s29gl01gp", "cfi-flash"; 42*4882a593Smuzhiyun reg = <0 0x00000000 0x08000000 43*4882a593Smuzhiyun 0 0x08000000 0x08000000>; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <1>; 46*4882a593Smuzhiyun bank-width = <4>; 47*4882a593Smuzhiyun device-width = <2>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun partition@0 { 50*4882a593Smuzhiyun label = "u-boot"; 51*4882a593Smuzhiyun reg = <0x00000000 0x00080000>; 52*4882a593Smuzhiyun read-only; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun partition@80000 { 55*4882a593Smuzhiyun label = "environment"; 56*4882a593Smuzhiyun reg = <0x00080000 0x00080000>; 57*4882a593Smuzhiyun read-only; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun partition@100000 { 60*4882a593Smuzhiyun label = "splash-image"; 61*4882a593Smuzhiyun reg = <0x00100000 0x00080000>; 62*4882a593Smuzhiyun read-only; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun partition@180000 { 65*4882a593Smuzhiyun label = "device-tree"; 66*4882a593Smuzhiyun reg = <0x00180000 0x00040000>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun partition@1c0000 { 69*4882a593Smuzhiyun label = "kernel"; 70*4882a593Smuzhiyun reg = <0x001c0000 0x00500000>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun partition@6c0000 { 73*4882a593Smuzhiyun label = "filesystem"; 74*4882a593Smuzhiyun reg = <0x006c0000 0x07940000>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mram0@2,0 { 79*4882a593Smuzhiyun compatible = "mtd-ram"; 80*4882a593Smuzhiyun reg = <2 0x00000 0x10000>; 81*4882a593Smuzhiyun bank-width = <2>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun mram1@2,10000 { 85*4882a593Smuzhiyun compatible = "mtd-ram"; 86*4882a593Smuzhiyun reg = <2 0x010000 0x10000>; 87*4882a593Smuzhiyun bank-width = <2>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun soc@80000000 { 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun i2c@1700 { 94*4882a593Smuzhiyun fsl,preserve-clocking; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun eeprom@50 { 97*4882a593Smuzhiyun compatible = "atmel,24c01"; 98*4882a593Smuzhiyun reg = <0x50>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun rtc@68 { 102*4882a593Smuzhiyun compatible = "st,m41t00"; 103*4882a593Smuzhiyun reg = <0x68>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun i2c@1720 { 108*4882a593Smuzhiyun status = "disabled"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun i2c@1740 { 112*4882a593Smuzhiyun fsl,preserve-clocking; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun ethernet@2800 { 116*4882a593Smuzhiyun phy-handle = <&phy0>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun mdio@2800 { 120*4882a593Smuzhiyun phy0: ethernet-phy@1f { 121*4882a593Smuzhiyun compatible = "smsc,lan8700"; 122*4882a593Smuzhiyun reg = <0x1f>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* USB1 using external ULPI PHY */ 127*4882a593Smuzhiyun usb@3000 { 128*4882a593Smuzhiyun dr_mode = "host"; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* USB0 using internal UTMI PHY */ 132*4882a593Smuzhiyun usb@4000 { 133*4882a593Smuzhiyun fsl,invert-pwr-fault; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun psc@11000 { 137*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun psc@11100 { 141*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun psc@11200 { 145*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun psc@11300 { 149*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun psc@11400 { 153*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun psc@11500 { 157*4882a593Smuzhiyun status = "disabled"; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun psc@11600 { 161*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun psc@11700 { 165*4882a593Smuzhiyun status = "disabled"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun psc@11800 { 169*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun psc@11900 { 173*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc"; 174*4882a593Smuzhiyun #address-cells = <1>; 175*4882a593Smuzhiyun #size-cells = <0>; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* ADS7845 touch screen controller */ 178*4882a593Smuzhiyun ts@0 { 179*4882a593Smuzhiyun compatible = "ti,ads7846"; 180*4882a593Smuzhiyun reg = <0x0>; 181*4882a593Smuzhiyun spi-max-frequency = <3000000>; 182*4882a593Smuzhiyun /* pen irq is GPIO25 */ 183*4882a593Smuzhiyun interrupts = <78 0x8>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun psc@11a00 { 188*4882a593Smuzhiyun status = "disabled"; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun psc@11b00 { 192*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun}; 196