1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree Source for Motorola/Emerson MVME5100. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2013 CSC Australia Pty. Ltd. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without 8*4882a593Smuzhiyun * any warranty of any kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "MVME5100"; 15*4882a593Smuzhiyun compatible = "MVME5100"; 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <1>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun serial0 = &serial0; 21*4882a593Smuzhiyun pci0 = &pci0; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpus { 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun PowerPC,7410 { 29*4882a593Smuzhiyun device_type = "cpu"; 30*4882a593Smuzhiyun reg = <0x0>; 31*4882a593Smuzhiyun /* Following required by dtc but not used */ 32*4882a593Smuzhiyun d-cache-line-size = <32>; 33*4882a593Smuzhiyun i-cache-line-size = <32>; 34*4882a593Smuzhiyun i-cache-size = <32768>; 35*4882a593Smuzhiyun d-cache-size = <32768>; 36*4882a593Smuzhiyun timebase-frequency = <25000000>; 37*4882a593Smuzhiyun clock-frequency = <500000000>; 38*4882a593Smuzhiyun bus-frequency = <100000000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun memory { 43*4882a593Smuzhiyun device_type = "memory"; 44*4882a593Smuzhiyun reg = <0x0 0x20000000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun hawk@fef80000 { 48*4882a593Smuzhiyun #address-cells = <1>; 49*4882a593Smuzhiyun #size-cells = <1>; 50*4882a593Smuzhiyun compatible = "hawk-bridge", "simple-bus"; 51*4882a593Smuzhiyun ranges = <0x0 0xfef80000 0x10000>; 52*4882a593Smuzhiyun reg = <0xfef80000 0x10000>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun serial0: serial@8000 { 55*4882a593Smuzhiyun device_type = "serial"; 56*4882a593Smuzhiyun compatible = "ns16550"; 57*4882a593Smuzhiyun reg = <0x8000 0x80>; 58*4882a593Smuzhiyun reg-shift = <4>; 59*4882a593Smuzhiyun clock-frequency = <1843200>; 60*4882a593Smuzhiyun current-speed = <9600>; 61*4882a593Smuzhiyun interrupts = <1 1>; // IRQ1 Level Active Low. 62*4882a593Smuzhiyun interrupt-parent = <&mpic>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun serial1: serial@8200 { 66*4882a593Smuzhiyun device_type = "serial"; 67*4882a593Smuzhiyun compatible = "ns16550"; 68*4882a593Smuzhiyun reg = <0x8200 0x80>; 69*4882a593Smuzhiyun reg-shift = <4>; 70*4882a593Smuzhiyun clock-frequency = <1843200>; 71*4882a593Smuzhiyun current-speed = <9600>; 72*4882a593Smuzhiyun interrupts = <1 1>; // IRQ1 Level Active Low. 73*4882a593Smuzhiyun interrupt-parent = <&mpic>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun mpic: interrupt-controller@f3f80000 { 77*4882a593Smuzhiyun #interrupt-cells = <2>; 78*4882a593Smuzhiyun #address-cells = <0>; 79*4882a593Smuzhiyun device_type = "open-pic"; 80*4882a593Smuzhiyun compatible = "chrp,open-pic"; 81*4882a593Smuzhiyun interrupt-controller; 82*4882a593Smuzhiyun reg = <0xf3f80000 0x40000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pci0: pci@feff0000 { 87*4882a593Smuzhiyun #address-cells = <3>; 88*4882a593Smuzhiyun #size-cells = <2>; 89*4882a593Smuzhiyun #interrupt-cells = <1>; 90*4882a593Smuzhiyun device_type = "pci"; 91*4882a593Smuzhiyun compatible = "hawk-pci"; 92*4882a593Smuzhiyun reg = <0xfec00000 0x400000>; 93*4882a593Smuzhiyun 8259-interrupt-acknowledge = <0xfeff0030>; 94*4882a593Smuzhiyun ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0x800000 95*4882a593Smuzhiyun 0x2000000 0x0 0x80000000 0x80000000 0x0 0x74000000>; 96*4882a593Smuzhiyun bus-range = <0 255>; 97*4882a593Smuzhiyun clock-frequency = <33333333>; 98*4882a593Smuzhiyun interrupt-parent = <&mpic>; 99*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 100*4882a593Smuzhiyun interrupt-map = < 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * This definition (IDSEL 11) duplicates the 104*4882a593Smuzhiyun * interrupts definition in the i8259 105*4882a593Smuzhiyun * interrupt controller below. 106*4882a593Smuzhiyun * 107*4882a593Smuzhiyun * Do not change the interrupt sense/polarity from 108*4882a593Smuzhiyun * 0x2 to anything else, doing so will cause endless 109*4882a593Smuzhiyun * "spurious" i8259 interrupts to be fielded. 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun // IDSEL 11 - iPMC712 PCI/ISA Bridge 112*4882a593Smuzhiyun 0x5800 0x0 0x0 0x1 &mpic 0x0 0x2 113*4882a593Smuzhiyun 0x5800 0x0 0x0 0x2 &mpic 0x0 0x2 114*4882a593Smuzhiyun 0x5800 0x0 0x0 0x3 &mpic 0x0 0x2 115*4882a593Smuzhiyun 0x5800 0x0 0x0 0x4 &mpic 0x0 0x2 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* IDSEL 12 - Not Used */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* IDSEL 13 - Universe VME Bridge */ 120*4882a593Smuzhiyun 0x6800 0x0 0x0 0x1 &mpic 0x5 0x1 121*4882a593Smuzhiyun 0x6800 0x0 0x0 0x2 &mpic 0x6 0x1 122*4882a593Smuzhiyun 0x6800 0x0 0x0 0x3 &mpic 0x7 0x1 123*4882a593Smuzhiyun 0x6800 0x0 0x0 0x4 &mpic 0x8 0x1 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* IDSEL 14 - ENET 1 */ 126*4882a593Smuzhiyun 0x7000 0x0 0x0 0x1 &mpic 0x2 0x1 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* IDSEL 15 - Not Used */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* IDSEL 16 - PMC Slot 1 */ 131*4882a593Smuzhiyun 0x8000 0x0 0x0 0x1 &mpic 0x9 0x1 132*4882a593Smuzhiyun 0x8000 0x0 0x0 0x2 &mpic 0xa 0x1 133*4882a593Smuzhiyun 0x8000 0x0 0x0 0x3 &mpic 0xb 0x1 134*4882a593Smuzhiyun 0x8000 0x0 0x0 0x4 &mpic 0xc 0x1 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* IDSEL 17 - PMC Slot 2 */ 137*4882a593Smuzhiyun 0x8800 0x0 0x0 0x1 &mpic 0xc 0x1 138*4882a593Smuzhiyun 0x8800 0x0 0x0 0x2 &mpic 0x9 0x1 139*4882a593Smuzhiyun 0x8800 0x0 0x0 0x3 &mpic 0xa 0x1 140*4882a593Smuzhiyun 0x8800 0x0 0x0 0x4 &mpic 0xb 0x1 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* IDSEL 18 - Not Used */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* IDSEL 19 - ENET 2 */ 145*4882a593Smuzhiyun 0x9800 0x0 0x0 0x1 &mpic 0xd 0x1 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* IDSEL 20 - PMCSPAN (PCI-X) */ 148*4882a593Smuzhiyun 0xa000 0x0 0x0 0x1 &mpic 0x9 0x1 149*4882a593Smuzhiyun 0xa000 0x0 0x0 0x2 &mpic 0xa 0x1 150*4882a593Smuzhiyun 0xa000 0x0 0x0 0x3 &mpic 0xb 0x1 151*4882a593Smuzhiyun 0xa000 0x0 0x0 0x4 &mpic 0xc 0x1 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun >; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun isa { 156*4882a593Smuzhiyun #address-cells = <2>; 157*4882a593Smuzhiyun #size-cells = <1>; 158*4882a593Smuzhiyun #interrupt-cells = <2>; 159*4882a593Smuzhiyun device_type = "isa"; 160*4882a593Smuzhiyun compatible = "isa"; 161*4882a593Smuzhiyun ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>; 162*4882a593Smuzhiyun interrupt-parent = <&i8259>; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun i8259: interrupt-controller@20 { 165*4882a593Smuzhiyun #interrupt-cells = <2>; 166*4882a593Smuzhiyun #address-cells = <0>; 167*4882a593Smuzhiyun interrupts = <0 2>; 168*4882a593Smuzhiyun device_type = "interrupt-controller"; 169*4882a593Smuzhiyun compatible = "chrp,iic"; 170*4882a593Smuzhiyun interrupt-controller; 171*4882a593Smuzhiyun reg = <1 0x00000020 0x00000002 172*4882a593Smuzhiyun 1 0x000000a0 0x00000002 173*4882a593Smuzhiyun 1 0x000004d0 0x00000002>; 174*4882a593Smuzhiyun interrupt-parent = <&mpic>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun chosen { 182*4882a593Smuzhiyun stdout-path = &serial0; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun}; 186