1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8379E RDB Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007, 2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "fsl,mpc8379rdb"; 12*4882a593Smuzhiyun #address-cells = <1>; 13*4882a593Smuzhiyun #size-cells = <1>; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun ethernet0 = &enet0; 17*4882a593Smuzhiyun ethernet1 = &enet1; 18*4882a593Smuzhiyun serial0 = &serial0; 19*4882a593Smuzhiyun serial1 = &serial1; 20*4882a593Smuzhiyun pci0 = &pci0; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpus { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun PowerPC,8379@0 { 28*4882a593Smuzhiyun device_type = "cpu"; 29*4882a593Smuzhiyun reg = <0x0>; 30*4882a593Smuzhiyun d-cache-line-size = <32>; 31*4882a593Smuzhiyun i-cache-line-size = <32>; 32*4882a593Smuzhiyun d-cache-size = <32768>; 33*4882a593Smuzhiyun i-cache-size = <32768>; 34*4882a593Smuzhiyun timebase-frequency = <0>; 35*4882a593Smuzhiyun bus-frequency = <0>; 36*4882a593Smuzhiyun clock-frequency = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun memory { 41*4882a593Smuzhiyun device_type = "memory"; 42*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; // 256MB at 0 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun localbus@e0005000 { 46*4882a593Smuzhiyun #address-cells = <2>; 47*4882a593Smuzhiyun #size-cells = <1>; 48*4882a593Smuzhiyun compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 49*4882a593Smuzhiyun reg = <0xe0005000 0x1000>; 50*4882a593Smuzhiyun interrupts = <77 0x8>; 51*4882a593Smuzhiyun interrupt-parent = <&ipic>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun // CS0 and CS1 are swapped when 54*4882a593Smuzhiyun // booting from nand, but the 55*4882a593Smuzhiyun // addresses are the same. 56*4882a593Smuzhiyun ranges = <0x0 0x0 0xfe000000 0x00800000 57*4882a593Smuzhiyun 0x1 0x0 0xe0600000 0x00008000 58*4882a593Smuzhiyun 0x2 0x0 0xf0000000 0x00020000 59*4882a593Smuzhiyun 0x3 0x0 0xfa000000 0x00008000>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun flash@0,0 { 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <1>; 64*4882a593Smuzhiyun compatible = "cfi-flash"; 65*4882a593Smuzhiyun reg = <0x0 0x0 0x800000>; 66*4882a593Smuzhiyun bank-width = <2>; 67*4882a593Smuzhiyun device-width = <1>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun nand@1,0 { 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <1>; 73*4882a593Smuzhiyun compatible = "fsl,mpc8379-fcm-nand", 74*4882a593Smuzhiyun "fsl,elbc-fcm-nand"; 75*4882a593Smuzhiyun reg = <0x1 0x0 0x8000>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun u-boot@0 { 78*4882a593Smuzhiyun reg = <0x0 0x100000>; 79*4882a593Smuzhiyun read-only; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun kernel@100000 { 83*4882a593Smuzhiyun reg = <0x100000 0x300000>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun fs@400000 { 86*4882a593Smuzhiyun reg = <0x400000 0x1c00000>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun immr@e0000000 { 92*4882a593Smuzhiyun #address-cells = <1>; 93*4882a593Smuzhiyun #size-cells = <1>; 94*4882a593Smuzhiyun device_type = "soc"; 95*4882a593Smuzhiyun compatible = "simple-bus"; 96*4882a593Smuzhiyun ranges = <0x0 0xe0000000 0x00100000>; 97*4882a593Smuzhiyun reg = <0xe0000000 0x00000200>; 98*4882a593Smuzhiyun bus-frequency = <0>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun wdt@200 { 101*4882a593Smuzhiyun device_type = "watchdog"; 102*4882a593Smuzhiyun compatible = "mpc83xx_wdt"; 103*4882a593Smuzhiyun reg = <0x200 0x100>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun gpio1: gpio-controller@c00 { 107*4882a593Smuzhiyun #gpio-cells = <2>; 108*4882a593Smuzhiyun compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 109*4882a593Smuzhiyun reg = <0xc00 0x100>; 110*4882a593Smuzhiyun interrupts = <74 0x8>; 111*4882a593Smuzhiyun interrupt-parent = <&ipic>; 112*4882a593Smuzhiyun gpio-controller; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun gpio2: gpio-controller@d00 { 116*4882a593Smuzhiyun #gpio-cells = <2>; 117*4882a593Smuzhiyun compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio"; 118*4882a593Smuzhiyun reg = <0xd00 0x100>; 119*4882a593Smuzhiyun interrupts = <75 0x8>; 120*4882a593Smuzhiyun interrupt-parent = <&ipic>; 121*4882a593Smuzhiyun gpio-controller; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun sleep-nexus { 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun #size-cells = <1>; 127*4882a593Smuzhiyun compatible = "simple-bus"; 128*4882a593Smuzhiyun sleep = <&pmc 0x0c000000>; 129*4882a593Smuzhiyun ranges; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun i2c@3000 { 132*4882a593Smuzhiyun #address-cells = <1>; 133*4882a593Smuzhiyun #size-cells = <0>; 134*4882a593Smuzhiyun cell-index = <0>; 135*4882a593Smuzhiyun compatible = "fsl-i2c"; 136*4882a593Smuzhiyun reg = <0x3000 0x100>; 137*4882a593Smuzhiyun interrupts = <14 0x8>; 138*4882a593Smuzhiyun interrupt-parent = <&ipic>; 139*4882a593Smuzhiyun dfsrr; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun dtt@48 { 142*4882a593Smuzhiyun compatible = "national,lm75"; 143*4882a593Smuzhiyun reg = <0x48>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun at24@50 { 147*4882a593Smuzhiyun compatible = "atmel,24c256"; 148*4882a593Smuzhiyun reg = <0x50>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun rtc@68 { 152*4882a593Smuzhiyun compatible = "dallas,ds1339"; 153*4882a593Smuzhiyun reg = <0x68>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun mcu_pio: mcu@a { 157*4882a593Smuzhiyun #gpio-cells = <2>; 158*4882a593Smuzhiyun compatible = "fsl,mc9s08qg8-mpc8379erdb", 159*4882a593Smuzhiyun "fsl,mcu-mpc8349emitx"; 160*4882a593Smuzhiyun reg = <0x0a>; 161*4882a593Smuzhiyun gpio-controller; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun sdhci@2e000 { 166*4882a593Smuzhiyun compatible = "fsl,mpc8379-esdhc", "fsl,esdhc"; 167*4882a593Smuzhiyun reg = <0x2e000 0x1000>; 168*4882a593Smuzhiyun interrupts = <42 0x8>; 169*4882a593Smuzhiyun interrupt-parent = <&ipic>; 170*4882a593Smuzhiyun sdhci,wp-inverted; 171*4882a593Smuzhiyun /* Filled in by U-Boot */ 172*4882a593Smuzhiyun clock-frequency = <111111111>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun i2c@3100 { 177*4882a593Smuzhiyun #address-cells = <1>; 178*4882a593Smuzhiyun #size-cells = <0>; 179*4882a593Smuzhiyun cell-index = <1>; 180*4882a593Smuzhiyun compatible = "fsl-i2c"; 181*4882a593Smuzhiyun reg = <0x3100 0x100>; 182*4882a593Smuzhiyun interrupts = <15 0x8>; 183*4882a593Smuzhiyun interrupt-parent = <&ipic>; 184*4882a593Smuzhiyun dfsrr; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun spi@7000 { 188*4882a593Smuzhiyun cell-index = <0>; 189*4882a593Smuzhiyun compatible = "fsl,spi"; 190*4882a593Smuzhiyun reg = <0x7000 0x1000>; 191*4882a593Smuzhiyun interrupts = <16 0x8>; 192*4882a593Smuzhiyun interrupt-parent = <&ipic>; 193*4882a593Smuzhiyun mode = "cpu"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun dma@82a8 { 197*4882a593Smuzhiyun #address-cells = <1>; 198*4882a593Smuzhiyun #size-cells = <1>; 199*4882a593Smuzhiyun compatible = "fsl,mpc8379-dma", "fsl,elo-dma"; 200*4882a593Smuzhiyun reg = <0x82a8 4>; 201*4882a593Smuzhiyun ranges = <0 0x8100 0x1a8>; 202*4882a593Smuzhiyun interrupt-parent = <&ipic>; 203*4882a593Smuzhiyun interrupts = <71 8>; 204*4882a593Smuzhiyun cell-index = <0>; 205*4882a593Smuzhiyun dma-channel@0 { 206*4882a593Smuzhiyun compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 207*4882a593Smuzhiyun reg = <0 0x80>; 208*4882a593Smuzhiyun cell-index = <0>; 209*4882a593Smuzhiyun interrupt-parent = <&ipic>; 210*4882a593Smuzhiyun interrupts = <71 8>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun dma-channel@80 { 213*4882a593Smuzhiyun compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 214*4882a593Smuzhiyun reg = <0x80 0x80>; 215*4882a593Smuzhiyun cell-index = <1>; 216*4882a593Smuzhiyun interrupt-parent = <&ipic>; 217*4882a593Smuzhiyun interrupts = <71 8>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun dma-channel@100 { 220*4882a593Smuzhiyun compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 221*4882a593Smuzhiyun reg = <0x100 0x80>; 222*4882a593Smuzhiyun cell-index = <2>; 223*4882a593Smuzhiyun interrupt-parent = <&ipic>; 224*4882a593Smuzhiyun interrupts = <71 8>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun dma-channel@180 { 227*4882a593Smuzhiyun compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel"; 228*4882a593Smuzhiyun reg = <0x180 0x28>; 229*4882a593Smuzhiyun cell-index = <3>; 230*4882a593Smuzhiyun interrupt-parent = <&ipic>; 231*4882a593Smuzhiyun interrupts = <71 8>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun usb@23000 { 236*4882a593Smuzhiyun compatible = "fsl-usb2-dr"; 237*4882a593Smuzhiyun reg = <0x23000 0x1000>; 238*4882a593Smuzhiyun #address-cells = <1>; 239*4882a593Smuzhiyun #size-cells = <0>; 240*4882a593Smuzhiyun interrupt-parent = <&ipic>; 241*4882a593Smuzhiyun interrupts = <38 0x8>; 242*4882a593Smuzhiyun phy_type = "ulpi"; 243*4882a593Smuzhiyun sleep = <&pmc 0x00c00000>; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun enet0: ethernet@24000 { 247*4882a593Smuzhiyun #address-cells = <1>; 248*4882a593Smuzhiyun #size-cells = <1>; 249*4882a593Smuzhiyun cell-index = <0>; 250*4882a593Smuzhiyun device_type = "network"; 251*4882a593Smuzhiyun model = "eTSEC"; 252*4882a593Smuzhiyun compatible = "gianfar"; 253*4882a593Smuzhiyun reg = <0x24000 0x1000>; 254*4882a593Smuzhiyun ranges = <0x0 0x24000 0x1000>; 255*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 256*4882a593Smuzhiyun interrupts = <32 0x8 33 0x8 34 0x8>; 257*4882a593Smuzhiyun phy-connection-type = "mii"; 258*4882a593Smuzhiyun interrupt-parent = <&ipic>; 259*4882a593Smuzhiyun tbi-handle = <&tbi0>; 260*4882a593Smuzhiyun phy-handle = <&phy2>; 261*4882a593Smuzhiyun sleep = <&pmc 0xc0000000>; 262*4882a593Smuzhiyun fsl,magic-packet; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun mdio@520 { 265*4882a593Smuzhiyun #address-cells = <1>; 266*4882a593Smuzhiyun #size-cells = <0>; 267*4882a593Smuzhiyun compatible = "fsl,gianfar-mdio"; 268*4882a593Smuzhiyun reg = <0x520 0x20>; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun phy2: ethernet-phy@2 { 271*4882a593Smuzhiyun interrupt-parent = <&ipic>; 272*4882a593Smuzhiyun interrupts = <17 0x8>; 273*4882a593Smuzhiyun reg = <0x2>; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun tbi0: tbi-phy@11 { 277*4882a593Smuzhiyun reg = <0x11>; 278*4882a593Smuzhiyun device_type = "tbi-phy"; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun enet1: ethernet@25000 { 284*4882a593Smuzhiyun #address-cells = <1>; 285*4882a593Smuzhiyun #size-cells = <1>; 286*4882a593Smuzhiyun cell-index = <1>; 287*4882a593Smuzhiyun device_type = "network"; 288*4882a593Smuzhiyun model = "eTSEC"; 289*4882a593Smuzhiyun compatible = "gianfar"; 290*4882a593Smuzhiyun reg = <0x25000 0x1000>; 291*4882a593Smuzhiyun ranges = <0x0 0x25000 0x1000>; 292*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 293*4882a593Smuzhiyun interrupts = <35 0x8 36 0x8 37 0x8>; 294*4882a593Smuzhiyun phy-connection-type = "mii"; 295*4882a593Smuzhiyun interrupt-parent = <&ipic>; 296*4882a593Smuzhiyun fixed-link = <1 1 1000 0 0>; 297*4882a593Smuzhiyun tbi-handle = <&tbi1>; 298*4882a593Smuzhiyun sleep = <&pmc 0x30000000>; 299*4882a593Smuzhiyun fsl,magic-packet; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun mdio@520 { 302*4882a593Smuzhiyun #address-cells = <1>; 303*4882a593Smuzhiyun #size-cells = <0>; 304*4882a593Smuzhiyun compatible = "fsl,gianfar-tbi"; 305*4882a593Smuzhiyun reg = <0x520 0x20>; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun tbi1: tbi-phy@11 { 308*4882a593Smuzhiyun reg = <0x11>; 309*4882a593Smuzhiyun device_type = "tbi-phy"; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun serial0: serial@4500 { 315*4882a593Smuzhiyun cell-index = <0>; 316*4882a593Smuzhiyun device_type = "serial"; 317*4882a593Smuzhiyun compatible = "fsl,ns16550", "ns16550"; 318*4882a593Smuzhiyun reg = <0x4500 0x100>; 319*4882a593Smuzhiyun clock-frequency = <0>; 320*4882a593Smuzhiyun interrupts = <9 0x8>; 321*4882a593Smuzhiyun interrupt-parent = <&ipic>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun serial1: serial@4600 { 325*4882a593Smuzhiyun cell-index = <1>; 326*4882a593Smuzhiyun device_type = "serial"; 327*4882a593Smuzhiyun compatible = "fsl,ns16550", "ns16550"; 328*4882a593Smuzhiyun reg = <0x4600 0x100>; 329*4882a593Smuzhiyun clock-frequency = <0>; 330*4882a593Smuzhiyun interrupts = <10 0x8>; 331*4882a593Smuzhiyun interrupt-parent = <&ipic>; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun crypto@30000 { 335*4882a593Smuzhiyun compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 336*4882a593Smuzhiyun "fsl,sec2.1", "fsl,sec2.0"; 337*4882a593Smuzhiyun reg = <0x30000 0x10000>; 338*4882a593Smuzhiyun interrupts = <11 0x8>; 339*4882a593Smuzhiyun interrupt-parent = <&ipic>; 340*4882a593Smuzhiyun fsl,num-channels = <4>; 341*4882a593Smuzhiyun fsl,channel-fifo-len = <24>; 342*4882a593Smuzhiyun fsl,exec-units-mask = <0x9fe>; 343*4882a593Smuzhiyun fsl,descriptor-types-mask = <0x3ab0ebf>; 344*4882a593Smuzhiyun sleep = <&pmc 0x03000000>; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun sata@18000 { 348*4882a593Smuzhiyun compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 349*4882a593Smuzhiyun reg = <0x18000 0x1000>; 350*4882a593Smuzhiyun interrupts = <44 0x8>; 351*4882a593Smuzhiyun interrupt-parent = <&ipic>; 352*4882a593Smuzhiyun sleep = <&pmc 0x000000c0>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun sata@19000 { 356*4882a593Smuzhiyun compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 357*4882a593Smuzhiyun reg = <0x19000 0x1000>; 358*4882a593Smuzhiyun interrupts = <45 0x8>; 359*4882a593Smuzhiyun interrupt-parent = <&ipic>; 360*4882a593Smuzhiyun sleep = <&pmc 0x00000030>; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun sata@1a000 { 364*4882a593Smuzhiyun compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 365*4882a593Smuzhiyun reg = <0x1a000 0x1000>; 366*4882a593Smuzhiyun interrupts = <46 0x8>; 367*4882a593Smuzhiyun interrupt-parent = <&ipic>; 368*4882a593Smuzhiyun sleep = <&pmc 0x0000000c>; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun sata@1b000 { 372*4882a593Smuzhiyun compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 373*4882a593Smuzhiyun reg = <0x1b000 0x1000>; 374*4882a593Smuzhiyun interrupts = <47 0x8>; 375*4882a593Smuzhiyun interrupt-parent = <&ipic>; 376*4882a593Smuzhiyun sleep = <&pmc 0x00000003>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* IPIC 380*4882a593Smuzhiyun * interrupts cell = <intr #, sense> 381*4882a593Smuzhiyun * sense values match linux IORESOURCE_IRQ_* defines: 382*4882a593Smuzhiyun * sense == 8: Level, low assertion 383*4882a593Smuzhiyun * sense == 2: Edge, high-to-low change 384*4882a593Smuzhiyun */ 385*4882a593Smuzhiyun ipic: interrupt-controller@700 { 386*4882a593Smuzhiyun compatible = "fsl,ipic"; 387*4882a593Smuzhiyun interrupt-controller; 388*4882a593Smuzhiyun #address-cells = <0>; 389*4882a593Smuzhiyun #interrupt-cells = <2>; 390*4882a593Smuzhiyun reg = <0x700 0x100>; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun pmc: power@b00 { 394*4882a593Smuzhiyun compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc"; 395*4882a593Smuzhiyun reg = <0xb00 0x100 0xa00 0x100>; 396*4882a593Smuzhiyun interrupts = <80 0x8>; 397*4882a593Smuzhiyun interrupt-parent = <&ipic>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun pci0: pci@e0008500 { 402*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 403*4882a593Smuzhiyun interrupt-map = < 404*4882a593Smuzhiyun /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* IDSEL AD14 IRQ6 inta */ 407*4882a593Smuzhiyun 0x7000 0x0 0x0 0x1 &ipic 22 0x8 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 410*4882a593Smuzhiyun 0x7800 0x0 0x0 0x1 &ipic 21 0x8 411*4882a593Smuzhiyun 0x7800 0x0 0x0 0x2 &ipic 22 0x8 412*4882a593Smuzhiyun 0x7800 0x0 0x0 0x4 &ipic 23 0x8 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 415*4882a593Smuzhiyun 0xE000 0x0 0x0 0x1 &ipic 23 0x8 416*4882a593Smuzhiyun 0xE000 0x0 0x0 0x2 &ipic 21 0x8 417*4882a593Smuzhiyun 0xE000 0x0 0x0 0x3 &ipic 22 0x8>; 418*4882a593Smuzhiyun interrupt-parent = <&ipic>; 419*4882a593Smuzhiyun interrupts = <66 0x8>; 420*4882a593Smuzhiyun bus-range = <0x0 0x0>; 421*4882a593Smuzhiyun ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 422*4882a593Smuzhiyun 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 423*4882a593Smuzhiyun 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 424*4882a593Smuzhiyun sleep = <&pmc 0x00010000>; 425*4882a593Smuzhiyun clock-frequency = <66666666>; 426*4882a593Smuzhiyun #interrupt-cells = <1>; 427*4882a593Smuzhiyun #size-cells = <2>; 428*4882a593Smuzhiyun #address-cells = <3>; 429*4882a593Smuzhiyun reg = <0xe0008500 0x100 /* internal registers */ 430*4882a593Smuzhiyun 0xe0008300 0x8>; /* config space access registers */ 431*4882a593Smuzhiyun compatible = "fsl,mpc8349-pci"; 432*4882a593Smuzhiyun device_type = "pci"; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun leds { 436*4882a593Smuzhiyun compatible = "gpio-leds"; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun pwr { 439*4882a593Smuzhiyun gpios = <&mcu_pio 0 0>; 440*4882a593Smuzhiyun default-state = "on"; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun hdd { 444*4882a593Smuzhiyun gpios = <&mcu_pio 1 0>; 445*4882a593Smuzhiyun linux,default-trigger = "disk-activity"; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun}; 449