1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC7448HPC2 (Taiga) board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2006, 2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun * 2006 Roy Zang <Roy Zang at freescale.com>. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "mpc7448hpc2"; 13*4882a593Smuzhiyun compatible = "mpc74xx"; 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun ethernet0 = &enet0; 19*4882a593Smuzhiyun ethernet1 = &enet1; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun serial0 = &serial0; 22*4882a593Smuzhiyun serial1 = &serial1; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun pci0 = &pci0; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun cpus { 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells =<0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun PowerPC,7448@0 { 32*4882a593Smuzhiyun device_type = "cpu"; 33*4882a593Smuzhiyun reg = <0x0>; 34*4882a593Smuzhiyun d-cache-line-size = <32>; // 32 bytes 35*4882a593Smuzhiyun i-cache-line-size = <32>; // 32 bytes 36*4882a593Smuzhiyun d-cache-size = <0x8000>; // L1, 32K bytes 37*4882a593Smuzhiyun i-cache-size = <0x8000>; // L1, 32K bytes 38*4882a593Smuzhiyun timebase-frequency = <0>; // 33 MHz, from uboot 39*4882a593Smuzhiyun clock-frequency = <0>; // From U-Boot 40*4882a593Smuzhiyun bus-frequency = <0>; // From U-Boot 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun memory { 45*4882a593Smuzhiyun device_type = "memory"; 46*4882a593Smuzhiyun reg = <0x0 0x20000000 // DDR2 512M at 0 47*4882a593Smuzhiyun >; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun tsi108@c0000000 { 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <1>; 53*4882a593Smuzhiyun device_type = "tsi-bridge"; 54*4882a593Smuzhiyun ranges = <0x0 0xc0000000 0x10000>; 55*4882a593Smuzhiyun reg = <0xc0000000 0x10000>; 56*4882a593Smuzhiyun bus-frequency = <0>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun i2c@7000 { 59*4882a593Smuzhiyun interrupt-parent = <&mpic>; 60*4882a593Smuzhiyun interrupts = <14 0>; 61*4882a593Smuzhiyun reg = <0x7000 0x400>; 62*4882a593Smuzhiyun device_type = "i2c"; 63*4882a593Smuzhiyun compatible = "tsi108-i2c"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun MDIO: mdio@6000 { 67*4882a593Smuzhiyun compatible = "tsi108-mdio"; 68*4882a593Smuzhiyun reg = <0x6000 0x50>; 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun phy8: ethernet-phy@8 { 73*4882a593Smuzhiyun interrupt-parent = <&mpic>; 74*4882a593Smuzhiyun interrupts = <2 1>; 75*4882a593Smuzhiyun reg = <0x8>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun phy9: ethernet-phy@9 { 79*4882a593Smuzhiyun interrupt-parent = <&mpic>; 80*4882a593Smuzhiyun interrupts = <2 1>; 81*4882a593Smuzhiyun reg = <0x9>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun enet0: ethernet@6200 { 87*4882a593Smuzhiyun linux,network-index = <0>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun device_type = "network"; 90*4882a593Smuzhiyun compatible = "tsi108-ethernet"; 91*4882a593Smuzhiyun reg = <0x6000 0x200>; 92*4882a593Smuzhiyun address = [ 00 06 D2 00 00 01 ]; 93*4882a593Smuzhiyun interrupts = <16 2>; 94*4882a593Smuzhiyun interrupt-parent = <&mpic>; 95*4882a593Smuzhiyun mdio-handle = <&MDIO>; 96*4882a593Smuzhiyun phy-handle = <&phy8>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun enet1: ethernet@6600 { 100*4882a593Smuzhiyun linux,network-index = <1>; 101*4882a593Smuzhiyun #address-cells = <1>; 102*4882a593Smuzhiyun #size-cells = <0>; 103*4882a593Smuzhiyun device_type = "network"; 104*4882a593Smuzhiyun compatible = "tsi108-ethernet"; 105*4882a593Smuzhiyun reg = <0x6400 0x200>; 106*4882a593Smuzhiyun address = [ 00 06 D2 00 00 02 ]; 107*4882a593Smuzhiyun interrupts = <17 2>; 108*4882a593Smuzhiyun interrupt-parent = <&mpic>; 109*4882a593Smuzhiyun mdio-handle = <&MDIO>; 110*4882a593Smuzhiyun phy-handle = <&phy9>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun serial0: serial@7808 { 114*4882a593Smuzhiyun device_type = "serial"; 115*4882a593Smuzhiyun compatible = "ns16550"; 116*4882a593Smuzhiyun reg = <0x7808 0x200>; 117*4882a593Smuzhiyun clock-frequency = <1064000000>; 118*4882a593Smuzhiyun interrupts = <12 0>; 119*4882a593Smuzhiyun interrupt-parent = <&mpic>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun serial1: serial@7c08 { 123*4882a593Smuzhiyun device_type = "serial"; 124*4882a593Smuzhiyun compatible = "ns16550"; 125*4882a593Smuzhiyun reg = <0x7c08 0x200>; 126*4882a593Smuzhiyun clock-frequency = <1064000000>; 127*4882a593Smuzhiyun interrupts = <13 0>; 128*4882a593Smuzhiyun interrupt-parent = <&mpic>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun mpic: pic@7400 { 132*4882a593Smuzhiyun interrupt-controller; 133*4882a593Smuzhiyun #address-cells = <0>; 134*4882a593Smuzhiyun #interrupt-cells = <2>; 135*4882a593Smuzhiyun reg = <0x7400 0x400>; 136*4882a593Smuzhiyun compatible = "chrp,open-pic"; 137*4882a593Smuzhiyun device_type = "open-pic"; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun pci0: pci@1000 { 140*4882a593Smuzhiyun compatible = "tsi108-pci"; 141*4882a593Smuzhiyun device_type = "pci"; 142*4882a593Smuzhiyun #interrupt-cells = <1>; 143*4882a593Smuzhiyun #size-cells = <2>; 144*4882a593Smuzhiyun #address-cells = <3>; 145*4882a593Smuzhiyun reg = <0x1000 0x1000>; 146*4882a593Smuzhiyun bus-range = <0 0>; 147*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000 148*4882a593Smuzhiyun 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>; 149*4882a593Smuzhiyun clock-frequency = <133333332>; 150*4882a593Smuzhiyun interrupt-parent = <&mpic>; 151*4882a593Smuzhiyun interrupts = <23 2>; 152*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 153*4882a593Smuzhiyun interrupt-map = < 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* IDSEL 0x11 */ 156*4882a593Smuzhiyun 0x800 0x0 0x0 0x1 &RT0 0x24 0x0 157*4882a593Smuzhiyun 0x800 0x0 0x0 0x2 &RT0 0x25 0x0 158*4882a593Smuzhiyun 0x800 0x0 0x0 0x3 &RT0 0x26 0x0 159*4882a593Smuzhiyun 0x800 0x0 0x0 0x4 &RT0 0x27 0x0 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* IDSEL 0x12 */ 162*4882a593Smuzhiyun 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0 163*4882a593Smuzhiyun 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0 164*4882a593Smuzhiyun 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0 165*4882a593Smuzhiyun 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* IDSEL 0x13 */ 168*4882a593Smuzhiyun 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0 169*4882a593Smuzhiyun 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0 170*4882a593Smuzhiyun 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0 171*4882a593Smuzhiyun 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun /* IDSEL 0x14 */ 174*4882a593Smuzhiyun 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0 175*4882a593Smuzhiyun 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0 176*4882a593Smuzhiyun 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0 177*4882a593Smuzhiyun 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0 178*4882a593Smuzhiyun >; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun RT0: router@1180 { 181*4882a593Smuzhiyun clock-frequency = <0>; 182*4882a593Smuzhiyun interrupt-controller; 183*4882a593Smuzhiyun device_type = "pic-router"; 184*4882a593Smuzhiyun #address-cells = <0>; 185*4882a593Smuzhiyun #interrupt-cells = <2>; 186*4882a593Smuzhiyun big-endian; 187*4882a593Smuzhiyun interrupts = <23 2>; 188*4882a593Smuzhiyun interrupt-parent = <&mpic>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193