1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC5121E ADS Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007-2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "mpc5121.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "mpc5121ads"; 12*4882a593Smuzhiyun compatible = "fsl,mpc5121ads", "fsl,mpc5121"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun nfc@40000000 { 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * ADS has two Hynix 512MB Nand flash chips in a single 17*4882a593Smuzhiyun * stacked package. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun chips = <2>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun nand@0 { 22*4882a593Smuzhiyun label = "nand"; 23*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; /* 512MB + 512MB */ 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun localbus@80000020 { 28*4882a593Smuzhiyun ranges = <0x0 0x0 0xfc000000 0x04000000 29*4882a593Smuzhiyun 0x2 0x0 0x82000000 0x00008000>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun flash@0,0 { 32*4882a593Smuzhiyun compatible = "cfi-flash"; 33*4882a593Smuzhiyun reg = <0 0x0 0x4000000>; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <1>; 36*4882a593Smuzhiyun bank-width = <4>; 37*4882a593Smuzhiyun device-width = <2>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun protected@0 { 40*4882a593Smuzhiyun label = "protected"; 41*4882a593Smuzhiyun reg = <0x00000000 0x00040000>; // first sector is protected 42*4882a593Smuzhiyun read-only; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun filesystem@40000 { 45*4882a593Smuzhiyun label = "filesystem"; 46*4882a593Smuzhiyun reg = <0x00040000 0x03c00000>; // 60M for filesystem 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun kernel@3c40000 { 49*4882a593Smuzhiyun label = "kernel"; 50*4882a593Smuzhiyun reg = <0x03c40000 0x00280000>; // 2.5M for kernel 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun device-tree@3ec0000 { 53*4882a593Smuzhiyun label = "device-tree"; 54*4882a593Smuzhiyun reg = <0x03ec0000 0x00040000>; // one sector for device tree 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun u-boot@3f00000 { 57*4882a593Smuzhiyun label = "u-boot"; 58*4882a593Smuzhiyun reg = <0x03f00000 0x00100000>; // 1M for u-boot 59*4882a593Smuzhiyun read-only; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun board-control@2,0 { 64*4882a593Smuzhiyun compatible = "fsl,mpc5121ads-cpld"; 65*4882a593Smuzhiyun reg = <0x2 0x0 0x8000>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun cpld_pic: pic@2,a { 69*4882a593Smuzhiyun compatible = "fsl,mpc5121ads-cpld-pic"; 70*4882a593Smuzhiyun interrupt-controller; 71*4882a593Smuzhiyun #interrupt-cells = <2>; 72*4882a593Smuzhiyun reg = <0x2 0xa 0x5>; 73*4882a593Smuzhiyun /* irq routing: 74*4882a593Smuzhiyun * all irqs but touch screen are routed to irq0 (ipic 48) 75*4882a593Smuzhiyun * touch screen is statically routed to irq1 (ipic 17) 76*4882a593Smuzhiyun * so don't use it here 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun interrupts = <48 0x8>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun soc@80000000 { 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun i2c@1700 { 85*4882a593Smuzhiyun fsl,preserve-clocking; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun hwmon@4a { 88*4882a593Smuzhiyun compatible = "adi,ad7414"; 89*4882a593Smuzhiyun reg = <0x4a>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun eeprom@50 { 93*4882a593Smuzhiyun compatible = "atmel,24c32"; 94*4882a593Smuzhiyun reg = <0x50>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun rtc@68 { 98*4882a593Smuzhiyun compatible = "st,m41t62"; 99*4882a593Smuzhiyun reg = <0x68>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun eth0: ethernet@2800 { 104*4882a593Smuzhiyun phy-handle = <&phy0>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun can@2300 { 108*4882a593Smuzhiyun status = "disabled"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun can@2380 { 112*4882a593Smuzhiyun status = "disabled"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun viu@2400 { 116*4882a593Smuzhiyun status = "disabled"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun mdio@2800 { 120*4882a593Smuzhiyun phy0: ethernet-phy@0 { 121*4882a593Smuzhiyun reg = <1>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* mpc5121ads only uses USB0 */ 126*4882a593Smuzhiyun usb@3000 { 127*4882a593Smuzhiyun status = "disabled"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* USB0 using internal UTMI PHY */ 131*4882a593Smuzhiyun usb@4000 { 132*4882a593Smuzhiyun dr_mode = "host"; 133*4882a593Smuzhiyun fsl,invert-drvvbus; 134*4882a593Smuzhiyun fsl,invert-pwr-fault; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* PSC3 serial port A aka ttyPSC0 */ 138*4882a593Smuzhiyun psc@11300 { 139*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* PSC4 serial port B aka ttyPSC1 */ 143*4882a593Smuzhiyun psc@11400 { 144*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* PSC5 in ac97 mode */ 148*4882a593Smuzhiyun ac97: psc@11500 { 149*4882a593Smuzhiyun compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc"; 150*4882a593Smuzhiyun fsl,mode = "ac97-slave"; 151*4882a593Smuzhiyun fsl,rx-fifo-size = <384>; 152*4882a593Smuzhiyun fsl,tx-fifo-size = <384>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun pci: pci@80008500 { 157*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 158*4882a593Smuzhiyun interrupt-map = < 159*4882a593Smuzhiyun /* IDSEL 0x15 - Slot 1 PCI */ 160*4882a593Smuzhiyun 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8 161*4882a593Smuzhiyun 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8 162*4882a593Smuzhiyun 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8 163*4882a593Smuzhiyun 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* IDSEL 0x16 - Slot 2 MiniPCI */ 166*4882a593Smuzhiyun 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8 167*4882a593Smuzhiyun 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* IDSEL 0x17 - Slot 3 MiniPCI */ 170*4882a593Smuzhiyun 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8 171*4882a593Smuzhiyun 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8 172*4882a593Smuzhiyun >; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun}; 175