1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree Source for AMCC Makalu (405EX) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without 8*4882a593Smuzhiyun * any warranty of any kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun #address-cells = <1>; 15*4882a593Smuzhiyun #size-cells = <1>; 16*4882a593Smuzhiyun model = "amcc,makalu"; 17*4882a593Smuzhiyun compatible = "amcc,makalu"; 18*4882a593Smuzhiyun dcr-parent = <&{/cpus/cpu@0}>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun aliases { 21*4882a593Smuzhiyun ethernet0 = &EMAC0; 22*4882a593Smuzhiyun ethernet1 = &EMAC1; 23*4882a593Smuzhiyun serial0 = &UART0; 24*4882a593Smuzhiyun serial1 = &UART1; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun cpus { 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpu@0 { 32*4882a593Smuzhiyun device_type = "cpu"; 33*4882a593Smuzhiyun model = "PowerPC,405EX"; 34*4882a593Smuzhiyun reg = <0x00000000>; 35*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 36*4882a593Smuzhiyun timebase-frequency = <0>; /* Filled in by U-Boot */ 37*4882a593Smuzhiyun i-cache-line-size = <32>; 38*4882a593Smuzhiyun d-cache-line-size = <32>; 39*4882a593Smuzhiyun i-cache-size = <16384>; /* 16 kB */ 40*4882a593Smuzhiyun d-cache-size = <16384>; /* 16 kB */ 41*4882a593Smuzhiyun dcr-controller; 42*4882a593Smuzhiyun dcr-access-method = "native"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun memory { 47*4882a593Smuzhiyun device_type = "memory"; 48*4882a593Smuzhiyun reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun UIC0: interrupt-controller { 52*4882a593Smuzhiyun compatible = "ibm,uic-405ex", "ibm,uic"; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun cell-index = <0>; 55*4882a593Smuzhiyun dcr-reg = <0x0c0 0x009>; 56*4882a593Smuzhiyun #address-cells = <0>; 57*4882a593Smuzhiyun #size-cells = <0>; 58*4882a593Smuzhiyun #interrupt-cells = <2>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun UIC1: interrupt-controller1 { 62*4882a593Smuzhiyun compatible = "ibm,uic-405ex","ibm,uic"; 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun cell-index = <1>; 65*4882a593Smuzhiyun dcr-reg = <0x0d0 0x009>; 66*4882a593Smuzhiyun #address-cells = <0>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun #interrupt-cells = <2>; 69*4882a593Smuzhiyun interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 70*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun UIC2: interrupt-controller2 { 74*4882a593Smuzhiyun compatible = "ibm,uic-405ex","ibm,uic"; 75*4882a593Smuzhiyun interrupt-controller; 76*4882a593Smuzhiyun cell-index = <2>; 77*4882a593Smuzhiyun dcr-reg = <0x0e0 0x009>; 78*4882a593Smuzhiyun #address-cells = <0>; 79*4882a593Smuzhiyun #size-cells = <0>; 80*4882a593Smuzhiyun #interrupt-cells = <2>; 81*4882a593Smuzhiyun interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 82*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun plb { 86*4882a593Smuzhiyun compatible = "ibm,plb-405ex", "ibm,plb4"; 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <1>; 89*4882a593Smuzhiyun ranges; 90*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun SDRAM0: memory-controller { 93*4882a593Smuzhiyun compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; 94*4882a593Smuzhiyun dcr-reg = <0x010 0x002>; 95*4882a593Smuzhiyun interrupt-parent = <&UIC2>; 96*4882a593Smuzhiyun interrupts = <0x5 0x4 /* ECC DED Error */ 97*4882a593Smuzhiyun 0x6 0x4 /* ECC SEC Error */ >; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun MAL0: mcmal { 101*4882a593Smuzhiyun compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 102*4882a593Smuzhiyun dcr-reg = <0x180 0x062>; 103*4882a593Smuzhiyun num-tx-chans = <2>; 104*4882a593Smuzhiyun num-rx-chans = <2>; 105*4882a593Smuzhiyun interrupt-parent = <&MAL0>; 106*4882a593Smuzhiyun interrupts = <0x0 0x1 0x2 0x3 0x4>; 107*4882a593Smuzhiyun #interrupt-cells = <1>; 108*4882a593Smuzhiyun #address-cells = <0>; 109*4882a593Smuzhiyun #size-cells = <0>; 110*4882a593Smuzhiyun interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 111*4882a593Smuzhiyun /*RXEOB*/ 0x1 &UIC0 0xb 0x4 112*4882a593Smuzhiyun /*SERR*/ 0x2 &UIC1 0x0 0x4 113*4882a593Smuzhiyun /*TXDE*/ 0x3 &UIC1 0x1 0x4 114*4882a593Smuzhiyun /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 115*4882a593Smuzhiyun interrupt-map-mask = <0xffffffff>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun POB0: opb { 119*4882a593Smuzhiyun compatible = "ibm,opb-405ex", "ibm,opb"; 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <1>; 122*4882a593Smuzhiyun ranges = <0x80000000 0x80000000 0x10000000 123*4882a593Smuzhiyun 0xef600000 0xef600000 0x00a00000 124*4882a593Smuzhiyun 0xf0000000 0xf0000000 0x10000000>; 125*4882a593Smuzhiyun dcr-reg = <0x0a0 0x005>; 126*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun EBC0: ebc { 129*4882a593Smuzhiyun compatible = "ibm,ebc-405ex", "ibm,ebc"; 130*4882a593Smuzhiyun dcr-reg = <0x012 0x002>; 131*4882a593Smuzhiyun #address-cells = <2>; 132*4882a593Smuzhiyun #size-cells = <1>; 133*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 134*4882a593Smuzhiyun /* ranges property is supplied by U-Boot */ 135*4882a593Smuzhiyun interrupts = <0x5 0x1>; 136*4882a593Smuzhiyun interrupt-parent = <&UIC1>; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun nor_flash@0,0 { 139*4882a593Smuzhiyun compatible = "amd,s29gl512n", "cfi-flash"; 140*4882a593Smuzhiyun bank-width = <2>; 141*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x04000000>; 142*4882a593Smuzhiyun #address-cells = <1>; 143*4882a593Smuzhiyun #size-cells = <1>; 144*4882a593Smuzhiyun partition@0 { 145*4882a593Smuzhiyun label = "kernel"; 146*4882a593Smuzhiyun reg = <0x00000000 0x00200000>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun partition@200000 { 149*4882a593Smuzhiyun label = "root"; 150*4882a593Smuzhiyun reg = <0x00200000 0x00200000>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun partition@400000 { 153*4882a593Smuzhiyun label = "user"; 154*4882a593Smuzhiyun reg = <0x00400000 0x03b60000>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun partition@3f60000 { 157*4882a593Smuzhiyun label = "env"; 158*4882a593Smuzhiyun reg = <0x03f60000 0x00040000>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun partition@3fa0000 { 161*4882a593Smuzhiyun label = "u-boot"; 162*4882a593Smuzhiyun reg = <0x03fa0000 0x00060000>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun UART0: serial@ef600200 { 168*4882a593Smuzhiyun device_type = "serial"; 169*4882a593Smuzhiyun compatible = "ns16550"; 170*4882a593Smuzhiyun reg = <0xef600200 0x00000008>; 171*4882a593Smuzhiyun virtual-reg = <0xef600200>; 172*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 173*4882a593Smuzhiyun current-speed = <0>; 174*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 175*4882a593Smuzhiyun interrupts = <0x1a 0x4>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun UART1: serial@ef600300 { 179*4882a593Smuzhiyun device_type = "serial"; 180*4882a593Smuzhiyun compatible = "ns16550"; 181*4882a593Smuzhiyun reg = <0xef600300 0x00000008>; 182*4882a593Smuzhiyun virtual-reg = <0xef600300>; 183*4882a593Smuzhiyun clock-frequency = <0>; /* Filled in by U-Boot */ 184*4882a593Smuzhiyun current-speed = <0>; 185*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 186*4882a593Smuzhiyun interrupts = <0x1 0x4>; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun IIC0: i2c@ef600400 { 190*4882a593Smuzhiyun compatible = "ibm,iic-405ex", "ibm,iic"; 191*4882a593Smuzhiyun reg = <0xef600400 0x00000014>; 192*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 193*4882a593Smuzhiyun interrupts = <0x2 0x4>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun IIC1: i2c@ef600500 { 197*4882a593Smuzhiyun compatible = "ibm,iic-405ex", "ibm,iic"; 198*4882a593Smuzhiyun reg = <0xef600500 0x00000014>; 199*4882a593Smuzhiyun interrupt-parent = <&UIC0>; 200*4882a593Smuzhiyun interrupts = <0x7 0x4>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun RGMII0: emac-rgmii@ef600b00 { 205*4882a593Smuzhiyun compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 206*4882a593Smuzhiyun reg = <0xef600b00 0x00000104>; 207*4882a593Smuzhiyun has-mdio; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun EMAC0: ethernet@ef600900 { 211*4882a593Smuzhiyun linux,network-index = <0x0>; 212*4882a593Smuzhiyun device_type = "network"; 213*4882a593Smuzhiyun compatible = "ibm,emac-405ex", "ibm,emac4sync"; 214*4882a593Smuzhiyun interrupt-parent = <&EMAC0>; 215*4882a593Smuzhiyun interrupts = <0x0 0x1>; 216*4882a593Smuzhiyun #interrupt-cells = <1>; 217*4882a593Smuzhiyun #address-cells = <0>; 218*4882a593Smuzhiyun #size-cells = <0>; 219*4882a593Smuzhiyun interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 220*4882a593Smuzhiyun /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 221*4882a593Smuzhiyun reg = <0xef600900 0x000000c4>; 222*4882a593Smuzhiyun local-mac-address = [000000000000]; /* Filled in by U-Boot */ 223*4882a593Smuzhiyun mal-device = <&MAL0>; 224*4882a593Smuzhiyun mal-tx-channel = <0>; 225*4882a593Smuzhiyun mal-rx-channel = <0>; 226*4882a593Smuzhiyun cell-index = <0>; 227*4882a593Smuzhiyun max-frame-size = <9000>; 228*4882a593Smuzhiyun rx-fifo-size = <4096>; 229*4882a593Smuzhiyun tx-fifo-size = <2048>; 230*4882a593Smuzhiyun rx-fifo-size-gige = <16384>; 231*4882a593Smuzhiyun tx-fifo-size-gige = <16384>; 232*4882a593Smuzhiyun phy-mode = "rgmii"; 233*4882a593Smuzhiyun phy-map = <0x0000003f>; /* Start at 6 */ 234*4882a593Smuzhiyun rgmii-device = <&RGMII0>; 235*4882a593Smuzhiyun rgmii-channel = <0>; 236*4882a593Smuzhiyun has-inverted-stacr-oc; 237*4882a593Smuzhiyun has-new-stacr-staopc; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun EMAC1: ethernet@ef600a00 { 241*4882a593Smuzhiyun linux,network-index = <0x1>; 242*4882a593Smuzhiyun device_type = "network"; 243*4882a593Smuzhiyun compatible = "ibm,emac-405ex", "ibm,emac4sync"; 244*4882a593Smuzhiyun interrupt-parent = <&EMAC1>; 245*4882a593Smuzhiyun interrupts = <0x0 0x1>; 246*4882a593Smuzhiyun #interrupt-cells = <1>; 247*4882a593Smuzhiyun #address-cells = <0>; 248*4882a593Smuzhiyun #size-cells = <0>; 249*4882a593Smuzhiyun interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 250*4882a593Smuzhiyun /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 251*4882a593Smuzhiyun reg = <0xef600a00 0x000000c4>; 252*4882a593Smuzhiyun local-mac-address = [000000000000]; /* Filled in by U-Boot */ 253*4882a593Smuzhiyun mal-device = <&MAL0>; 254*4882a593Smuzhiyun mal-tx-channel = <1>; 255*4882a593Smuzhiyun mal-rx-channel = <1>; 256*4882a593Smuzhiyun cell-index = <1>; 257*4882a593Smuzhiyun max-frame-size = <9000>; 258*4882a593Smuzhiyun rx-fifo-size = <4096>; 259*4882a593Smuzhiyun tx-fifo-size = <2048>; 260*4882a593Smuzhiyun rx-fifo-size-gige = <16384>; 261*4882a593Smuzhiyun tx-fifo-size-gige = <16384>; 262*4882a593Smuzhiyun phy-mode = "rgmii"; 263*4882a593Smuzhiyun phy-map = <0x00000000>; 264*4882a593Smuzhiyun rgmii-device = <&RGMII0>; 265*4882a593Smuzhiyun rgmii-channel = <1>; 266*4882a593Smuzhiyun has-inverted-stacr-oc; 267*4882a593Smuzhiyun has-new-stacr-staopc; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun PCIE0: pcie@a0000000 { 272*4882a593Smuzhiyun device_type = "pci"; 273*4882a593Smuzhiyun #interrupt-cells = <1>; 274*4882a593Smuzhiyun #size-cells = <2>; 275*4882a593Smuzhiyun #address-cells = <3>; 276*4882a593Smuzhiyun compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 277*4882a593Smuzhiyun primary; 278*4882a593Smuzhiyun port = <0x0>; /* port number */ 279*4882a593Smuzhiyun reg = <0xa0000000 0x20000000 /* Config space access */ 280*4882a593Smuzhiyun 0xef000000 0x00001000>; /* Registers */ 281*4882a593Smuzhiyun dcr-reg = <0x040 0x020>; 282*4882a593Smuzhiyun sdr-base = <0x400>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* Outbound ranges, one memory and one IO, 285*4882a593Smuzhiyun * later cannot be changed 286*4882a593Smuzhiyun */ 287*4882a593Smuzhiyun ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 288*4882a593Smuzhiyun 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* Inbound 2GB range starting at 0 */ 291*4882a593Smuzhiyun dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /* This drives busses 0x00 to 0x3f */ 294*4882a593Smuzhiyun bus-range = <0x0 0x3f>; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* Legacy interrupts (note the weird polarity, the bridge seems 297*4882a593Smuzhiyun * to invert PCIe legacy interrupts). 298*4882a593Smuzhiyun * We are de-swizzling here because the numbers are actually for 299*4882a593Smuzhiyun * port of the root complex virtual P2P bridge. But I want 300*4882a593Smuzhiyun * to avoid putting a node for it in the tree, so the numbers 301*4882a593Smuzhiyun * below are basically de-swizzled numbers. 302*4882a593Smuzhiyun * The real slot is on idsel 0, so the swizzling is 1:1 303*4882a593Smuzhiyun */ 304*4882a593Smuzhiyun interrupt-map-mask = <0x0 0x0 0x0 0x7>; 305*4882a593Smuzhiyun interrupt-map = < 306*4882a593Smuzhiyun 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 307*4882a593Smuzhiyun 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 308*4882a593Smuzhiyun 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 309*4882a593Smuzhiyun 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun PCIE1: pcie@c0000000 { 313*4882a593Smuzhiyun device_type = "pci"; 314*4882a593Smuzhiyun #interrupt-cells = <1>; 315*4882a593Smuzhiyun #size-cells = <2>; 316*4882a593Smuzhiyun #address-cells = <3>; 317*4882a593Smuzhiyun compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 318*4882a593Smuzhiyun primary; 319*4882a593Smuzhiyun port = <0x1>; /* port number */ 320*4882a593Smuzhiyun reg = <0xc0000000 0x20000000 /* Config space access */ 321*4882a593Smuzhiyun 0xef001000 0x00001000>; /* Registers */ 322*4882a593Smuzhiyun dcr-reg = <0x060 0x020>; 323*4882a593Smuzhiyun sdr-base = <0x440>; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun /* Outbound ranges, one memory and one IO, 326*4882a593Smuzhiyun * later cannot be changed 327*4882a593Smuzhiyun */ 328*4882a593Smuzhiyun ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 329*4882a593Smuzhiyun 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* Inbound 2GB range starting at 0 */ 332*4882a593Smuzhiyun dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /* This drives busses 0x40 to 0x7f */ 335*4882a593Smuzhiyun bus-range = <0x40 0x7f>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* Legacy interrupts (note the weird polarity, the bridge seems 338*4882a593Smuzhiyun * to invert PCIe legacy interrupts). 339*4882a593Smuzhiyun * We are de-swizzling here because the numbers are actually for 340*4882a593Smuzhiyun * port of the root complex virtual P2P bridge. But I want 341*4882a593Smuzhiyun * to avoid putting a node for it in the tree, so the numbers 342*4882a593Smuzhiyun * below are basically de-swizzled numbers. 343*4882a593Smuzhiyun * The real slot is on idsel 0, so the swizzling is 1:1 344*4882a593Smuzhiyun */ 345*4882a593Smuzhiyun interrupt-map-mask = <0x0 0x0 0x0 0x7>; 346*4882a593Smuzhiyun interrupt-map = < 347*4882a593Smuzhiyun 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 348*4882a593Smuzhiyun 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 349*4882a593Smuzhiyun 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 350*4882a593Smuzhiyun 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun}; 354