1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Lite5200B board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2006-2007 Secret Lab Technologies Ltd. 6*4882a593Smuzhiyun * Grant Likely <grant.likely@secretlab.ca> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/include/ "mpc5200b.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&gpt0 { fsl,has-wdt; }; 12*4882a593Smuzhiyun&gpt2 { gpio-controller; }; 13*4882a593Smuzhiyun&gpt3 { gpio-controller; }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "fsl,lite5200b"; 17*4882a593Smuzhiyun compatible = "fsl,lite5200b"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun leds { 20*4882a593Smuzhiyun compatible = "gpio-leds"; 21*4882a593Smuzhiyun tmr2 { 22*4882a593Smuzhiyun gpios = <&gpt2 0 1>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun tmr3 { 25*4882a593Smuzhiyun gpios = <&gpt3 0 1>; 26*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun led1 { gpios = <&gpio_wkup 2 1>; }; 29*4882a593Smuzhiyun led2 { gpios = <&gpio_simple 3 1>; }; 30*4882a593Smuzhiyun led3 { gpios = <&gpio_wkup 3 1>; }; 31*4882a593Smuzhiyun led4 { gpios = <&gpio_simple 2 1>; }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun memory@0 { 35*4882a593Smuzhiyun reg = <0x00000000 0x10000000>; // 256MB 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun soc5200@f0000000 { 39*4882a593Smuzhiyun psc@2000 { // PSC1 40*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 41*4882a593Smuzhiyun cell-index = <0>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun psc@2200 { // PSC2 45*4882a593Smuzhiyun status = "disabled"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun psc@2400 { // PSC3 49*4882a593Smuzhiyun status = "disabled"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun psc@2600 { // PSC4 53*4882a593Smuzhiyun status = "disabled"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun psc@2800 { // PSC5 57*4882a593Smuzhiyun status = "disabled"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun psc@2c00 { // PSC6 61*4882a593Smuzhiyun status = "disabled"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun // PSC2 in ac97 mode example 65*4882a593Smuzhiyun //ac97@2200 { // PSC2 66*4882a593Smuzhiyun // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 67*4882a593Smuzhiyun // cell-index = <1>; 68*4882a593Smuzhiyun //}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun // PSC3 in CODEC mode example 71*4882a593Smuzhiyun //i2s@2400 { // PSC3 72*4882a593Smuzhiyun // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 73*4882a593Smuzhiyun // cell-index = <2>; 74*4882a593Smuzhiyun //}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun // PSC6 in spi mode example 77*4882a593Smuzhiyun //spi@2c00 { // PSC6 78*4882a593Smuzhiyun // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 79*4882a593Smuzhiyun // cell-index = <5>; 80*4882a593Smuzhiyun //}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun ethernet@3000 { 83*4882a593Smuzhiyun phy-handle = <&phy0>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun mdio@3000 { 87*4882a593Smuzhiyun phy0: ethernet-phy@0 { 88*4882a593Smuzhiyun reg = <0>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun i2c@3d40 { 93*4882a593Smuzhiyun eeprom@50 { 94*4882a593Smuzhiyun compatible = "atmel,24c02"; 95*4882a593Smuzhiyun reg = <0x50>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun sram@8000 { 100*4882a593Smuzhiyun compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 101*4882a593Smuzhiyun reg = <0x8000 0x4000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun pci@f0000d00 { 106*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 107*4882a593Smuzhiyun interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 108*4882a593Smuzhiyun 0xc000 0 0 2 &mpc5200_pic 1 1 3 109*4882a593Smuzhiyun 0xc000 0 0 3 &mpc5200_pic 1 2 3 110*4882a593Smuzhiyun 0xc000 0 0 4 &mpc5200_pic 1 3 3 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 113*4882a593Smuzhiyun 0xc800 0 0 2 &mpc5200_pic 1 2 3 114*4882a593Smuzhiyun 0xc800 0 0 3 &mpc5200_pic 1 3 3 115*4882a593Smuzhiyun 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 116*4882a593Smuzhiyun clock-frequency = <0>; // From boot loader 117*4882a593Smuzhiyun interrupts = <2 8 0 2 9 0 2 10 0>; 118*4882a593Smuzhiyun bus-range = <0 0>; 119*4882a593Smuzhiyun ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 120*4882a593Smuzhiyun 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 121*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun localbus { 125*4882a593Smuzhiyun ranges = <0 0 0xfe000000 0x02000000>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun flash@0,0 { 128*4882a593Smuzhiyun compatible = "cfi-flash"; 129*4882a593Smuzhiyun reg = <0 0 0x02000000>; 130*4882a593Smuzhiyun bank-width = <1>; 131*4882a593Smuzhiyun #size-cells = <1>; 132*4882a593Smuzhiyun #address-cells = <1>; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun partition@0 { 135*4882a593Smuzhiyun label = "kernel"; 136*4882a593Smuzhiyun reg = <0x00000000 0x00200000>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun partition@200000 { 139*4882a593Smuzhiyun label = "rootfs"; 140*4882a593Smuzhiyun reg = <0x00200000 0x01d00000>; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun partition@1f00000 { 143*4882a593Smuzhiyun label = "u-boot"; 144*4882a593Smuzhiyun reg = <0x01f00000 0x00060000>; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun partition@1f60000 { 147*4882a593Smuzhiyun label = "u-boot-env"; 148*4882a593Smuzhiyun reg = <0x01f60000 0x00020000>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun partition@1f80000 { 151*4882a593Smuzhiyun label = "dtb"; 152*4882a593Smuzhiyun reg = <0x01f80000 0x00080000>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun}; 158