1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * T1040D4RDB/T1042D4RDB Device Tree Source 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun/ { 36*4882a593Smuzhiyun reserved-memory { 37*4882a593Smuzhiyun #address-cells = <2>; 38*4882a593Smuzhiyun #size-cells = <2>; 39*4882a593Smuzhiyun ranges; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun bman_fbpr: bman-fbpr { 42*4882a593Smuzhiyun size = <0 0x1000000>; 43*4882a593Smuzhiyun alignment = <0 0x1000000>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun qman_fqd: qman-fqd { 46*4882a593Smuzhiyun size = <0 0x400000>; 47*4882a593Smuzhiyun alignment = <0 0x400000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun qman_pfdr: qman-pfdr { 50*4882a593Smuzhiyun size = <0 0x2000000>; 51*4882a593Smuzhiyun alignment = <0 0x2000000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun ifc: localbus@ffe124000 { 56*4882a593Smuzhiyun reg = <0xf 0xfe124000 0 0x2000>; 57*4882a593Smuzhiyun ranges = <0 0 0xf 0xe8000000 0x08000000 58*4882a593Smuzhiyun 2 0 0xf 0xff800000 0x00010000 59*4882a593Smuzhiyun 3 0 0xf 0xffdf0000 0x00008000>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun nor@0,0 { 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <1>; 64*4882a593Smuzhiyun compatible = "cfi-flash"; 65*4882a593Smuzhiyun reg = <0x0 0x0 0x8000000>; 66*4882a593Smuzhiyun bank-width = <2>; 67*4882a593Smuzhiyun device-width = <1>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun nand@2,0 { 71*4882a593Smuzhiyun #address-cells = <1>; 72*4882a593Smuzhiyun #size-cells = <1>; 73*4882a593Smuzhiyun compatible = "fsl,ifc-nand"; 74*4882a593Smuzhiyun reg = <0x2 0x0 0x10000>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun cpld@3,0 { 78*4882a593Smuzhiyun compatible = "fsl,t1040d4rdb-cpld"; 79*4882a593Smuzhiyun reg = <3 0 0x300>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun memory { 84*4882a593Smuzhiyun device_type = "memory"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun dcsr: dcsr@f00000000 { 88*4882a593Smuzhiyun ranges = <0x00000000 0xf 0x00000000 0x01072000>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun bportals: bman-portals@ff4000000 { 92*4882a593Smuzhiyun ranges = <0x0 0xf 0xf4000000 0x2000000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun qportals: qman-portals@ff6000000 { 96*4882a593Smuzhiyun ranges = <0x0 0xf 0xf6000000 0x2000000>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun soc: soc@ffe000000 { 100*4882a593Smuzhiyun ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 101*4882a593Smuzhiyun reg = <0xf 0xfe000000 0 0x00001000>; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun spi@110000 { 104*4882a593Smuzhiyun flash@0 { 105*4882a593Smuzhiyun #address-cells = <1>; 106*4882a593Smuzhiyun #size-cells = <1>; 107*4882a593Smuzhiyun compatible = "micron,n25q512ax3", "jedec,spi-nor"; 108*4882a593Smuzhiyun reg = <0>; 109*4882a593Smuzhiyun /* input clock */ 110*4882a593Smuzhiyun spi-max-frequency = <10000000>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun slic@1 { 113*4882a593Smuzhiyun compatible = "maxim,ds26522"; 114*4882a593Smuzhiyun reg = <1>; 115*4882a593Smuzhiyun spi-max-frequency = <2000000>; /* input clock */ 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun slic@2 { 118*4882a593Smuzhiyun compatible = "maxim,ds26522"; 119*4882a593Smuzhiyun reg = <2>; 120*4882a593Smuzhiyun spi-max-frequency = <2000000>; /* input clock */ 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun i2c@118000 { 124*4882a593Smuzhiyun hwmon@4c { 125*4882a593Smuzhiyun compatible = "adi,adt7461"; 126*4882a593Smuzhiyun reg = <0x4c>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun rtc@68 { 130*4882a593Smuzhiyun compatible = "dallas,ds1337"; 131*4882a593Smuzhiyun reg = <0x68>; 132*4882a593Smuzhiyun interrupts = <0x2 0x1 0 0>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun i2c@118100 { 137*4882a593Smuzhiyun mux@77 { 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * Child nodes of mux depend on which i2c 140*4882a593Smuzhiyun * devices are connected via the mini PCI 141*4882a593Smuzhiyun * connector slot1, the mini PCI connector 142*4882a593Smuzhiyun * slot2, the HDMI connector, and the PEX 143*4882a593Smuzhiyun * slot. Systems with such devices attached 144*4882a593Smuzhiyun * should provide a wrapper .dts file that 145*4882a593Smuzhiyun * includes this one, and adds those nodes 146*4882a593Smuzhiyun */ 147*4882a593Smuzhiyun compatible = "nxp,pca9546"; 148*4882a593Smuzhiyun reg = <0x77>; 149*4882a593Smuzhiyun #address-cells = <1>; 150*4882a593Smuzhiyun #size-cells = <0>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun pci0: pcie@ffe240000 { 157*4882a593Smuzhiyun reg = <0xf 0xfe240000 0 0x10000>; 158*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000 159*4882a593Smuzhiyun 0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>; 160*4882a593Smuzhiyun pcie@0 { 161*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 162*4882a593Smuzhiyun 0x02000000 0 0xe0000000 163*4882a593Smuzhiyun 0 0x10000000 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun 0x01000000 0 0x00000000 166*4882a593Smuzhiyun 0x01000000 0 0x00000000 167*4882a593Smuzhiyun 0 0x00010000>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun pci1: pcie@ffe250000 { 172*4882a593Smuzhiyun reg = <0xf 0xfe250000 0 0x10000>; 173*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 174*4882a593Smuzhiyun 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; 175*4882a593Smuzhiyun pcie@0 { 176*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 177*4882a593Smuzhiyun 0x02000000 0 0xe0000000 178*4882a593Smuzhiyun 0 0x10000000 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun 0x01000000 0 0x00000000 181*4882a593Smuzhiyun 0x01000000 0 0x00000000 182*4882a593Smuzhiyun 0 0x00010000>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun pci2: pcie@ffe260000 { 187*4882a593Smuzhiyun reg = <0xf 0xfe260000 0 0x10000>; 188*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 189*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 190*4882a593Smuzhiyun pcie@0 { 191*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 192*4882a593Smuzhiyun 0x02000000 0 0xe0000000 193*4882a593Smuzhiyun 0 0x10000000 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun 0x01000000 0 0x00000000 196*4882a593Smuzhiyun 0x01000000 0 0x00000000 197*4882a593Smuzhiyun 0 0x00010000>; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun pci3: pcie@ffe270000 { 202*4882a593Smuzhiyun reg = <0xf 0xfe270000 0 0x10000>; 203*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 204*4882a593Smuzhiyun 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 205*4882a593Smuzhiyun pcie@0 { 206*4882a593Smuzhiyun ranges = <0x02000000 0 0xe0000000 207*4882a593Smuzhiyun 0x02000000 0 0xe0000000 208*4882a593Smuzhiyun 0 0x10000000 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun 0x01000000 0 0x00000000 211*4882a593Smuzhiyun 0x01000000 0 0x00000000 212*4882a593Smuzhiyun 0 0x00010000>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun qe: qe@ffe140000 { 217*4882a593Smuzhiyun ranges = <0x0 0xf 0xfe140000 0x40000>; 218*4882a593Smuzhiyun reg = <0xf 0xfe140000 0 0x480>; 219*4882a593Smuzhiyun brg-frequency = <0>; 220*4882a593Smuzhiyun bus-frequency = <0>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun si1: si@700 { 223*4882a593Smuzhiyun compatible = "fsl,t1040-qe-si"; 224*4882a593Smuzhiyun reg = <0x700 0x80>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun siram1: siram@1000 { 228*4882a593Smuzhiyun compatible = "fsl,t1040-qe-siram"; 229*4882a593Smuzhiyun reg = <0x1000 0x800>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun ucc_hdlc: ucc@2000 { 233*4882a593Smuzhiyun compatible = "fsl,ucc-hdlc"; 234*4882a593Smuzhiyun rx-clock-name = "clk8"; 235*4882a593Smuzhiyun tx-clock-name = "clk9"; 236*4882a593Smuzhiyun fsl,rx-sync-clock = "rsync_pin"; 237*4882a593Smuzhiyun fsl,tx-sync-clock = "tsync_pin"; 238*4882a593Smuzhiyun fsl,tx-timeslot-mask = <0xfffffffe>; 239*4882a593Smuzhiyun fsl,rx-timeslot-mask = <0xfffffffe>; 240*4882a593Smuzhiyun fsl,tdm-framer-type = "e1"; 241*4882a593Smuzhiyun fsl,tdm-id = <0>; 242*4882a593Smuzhiyun fsl,siram-entry-id = <0>; 243*4882a593Smuzhiyun fsl,tdm-interface; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun ucc_serial: ucc@2200 { 247*4882a593Smuzhiyun compatible = "fsl,t1040-ucc-uart"; 248*4882a593Smuzhiyun port-number = <0>; 249*4882a593Smuzhiyun rx-clock-name = "brg2"; 250*4882a593Smuzhiyun tx-clock-name = "brg2"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun}; 254