1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * T1024 Silicon/SoC Device Tree Source (post include) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun#include "t1023si-post.dtsi" 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun/ { 38*4882a593Smuzhiyun aliases { 39*4882a593Smuzhiyun vga = &display; 40*4882a593Smuzhiyun display = &display; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun qe:qe@ffe140000 { 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <1>; 46*4882a593Smuzhiyun device_type = "qe"; 47*4882a593Smuzhiyun compatible = "fsl,qe"; 48*4882a593Smuzhiyun ranges = <0x0 0xf 0xfe140000 0x40000>; 49*4882a593Smuzhiyun reg = <0xf 0xfe140000 0 0x480>; 50*4882a593Smuzhiyun fsl,qe-num-riscs = <1>; 51*4882a593Smuzhiyun fsl,qe-num-snums = <28>; 52*4882a593Smuzhiyun brg-frequency = <0>; 53*4882a593Smuzhiyun bus-frequency = <0>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&soc { 58*4882a593Smuzhiyun display:display@180000 { 59*4882a593Smuzhiyun compatible = "fsl,t1024-diu", "fsl,diu"; 60*4882a593Smuzhiyun reg = <0x180000 1000>; 61*4882a593Smuzhiyun interrupts = <74 2 0 0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&qe { 66*4882a593Smuzhiyun qeic: interrupt-controller@80 { 67*4882a593Smuzhiyun interrupt-controller; 68*4882a593Smuzhiyun compatible = "fsl,qe-ic"; 69*4882a593Smuzhiyun #address-cells = <0>; 70*4882a593Smuzhiyun #interrupt-cells = <1>; 71*4882a593Smuzhiyun reg = <0x80 0x80>; 72*4882a593Smuzhiyun interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun ucc@2000 { 76*4882a593Smuzhiyun cell-index = <1>; 77*4882a593Smuzhiyun reg = <0x2000 0x200>; 78*4882a593Smuzhiyun interrupts = <32>; 79*4882a593Smuzhiyun interrupt-parent = <&qeic>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun ucc@2200 { 83*4882a593Smuzhiyun cell-index = <3>; 84*4882a593Smuzhiyun reg = <0x2200 0x200>; 85*4882a593Smuzhiyun interrupts = <34>; 86*4882a593Smuzhiyun interrupt-parent = <&qeic>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun muram@10000 { 90*4882a593Smuzhiyun #address-cells = <1>; 91*4882a593Smuzhiyun #size-cells = <1>; 92*4882a593Smuzhiyun compatible = "fsl,qe-muram", "fsl,cpm-muram"; 93*4882a593Smuzhiyun ranges = <0x0 0x10000 0x6000>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun data-only@0 { 96*4882a593Smuzhiyun compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; 97*4882a593Smuzhiyun reg = <0x0 0x6000>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101