1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunmpic: pic@40000 { 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #address-cells = <0>; 38*4882a593Smuzhiyun #interrupt-cells = <4>; 39*4882a593Smuzhiyun reg = <0x40000 0x40000>; 40*4882a593Smuzhiyun compatible = "fsl,mpic", "chrp,open-pic"; 41*4882a593Smuzhiyun device_type = "open-pic"; 42*4882a593Smuzhiyun clock-frequency = <0x0>; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyuntimer@41100 { 46*4882a593Smuzhiyun compatible = "fsl,mpic-global-timer"; 47*4882a593Smuzhiyun reg = <0x41100 0x100 0x41300 4>; 48*4882a593Smuzhiyun interrupts = <0 0 3 0 49*4882a593Smuzhiyun 1 0 3 0 50*4882a593Smuzhiyun 2 0 3 0 51*4882a593Smuzhiyun 3 0 3 0>; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunmsi0: msi@41600 { 55*4882a593Smuzhiyun compatible = "fsl,mpic-msi"; 56*4882a593Smuzhiyun reg = <0x41600 0x200 0x44140 4>; 57*4882a593Smuzhiyun msi-available-ranges = <0 0x100>; 58*4882a593Smuzhiyun interrupts = < 59*4882a593Smuzhiyun 0xe0 0 0 0 60*4882a593Smuzhiyun 0xe1 0 0 0 61*4882a593Smuzhiyun 0xe2 0 0 0 62*4882a593Smuzhiyun 0xe3 0 0 0 63*4882a593Smuzhiyun 0xe4 0 0 0 64*4882a593Smuzhiyun 0xe5 0 0 0 65*4882a593Smuzhiyun 0xe6 0 0 0 66*4882a593Smuzhiyun 0xe7 0 0 0>; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunmsi1: msi@41800 { 70*4882a593Smuzhiyun compatible = "fsl,mpic-msi"; 71*4882a593Smuzhiyun reg = <0x41800 0x200 0x45140 4>; 72*4882a593Smuzhiyun msi-available-ranges = <0 0x100>; 73*4882a593Smuzhiyun interrupts = < 74*4882a593Smuzhiyun 0xe8 0 0 0 75*4882a593Smuzhiyun 0xe9 0 0 0 76*4882a593Smuzhiyun 0xea 0 0 0 77*4882a593Smuzhiyun 0xeb 0 0 0 78*4882a593Smuzhiyun 0xec 0 0 0 79*4882a593Smuzhiyun 0xed 0 0 0 80*4882a593Smuzhiyun 0xee 0 0 0 81*4882a593Smuzhiyun 0xef 0 0 0>; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunmsi2: msi@41a00 { 85*4882a593Smuzhiyun compatible = "fsl,mpic-msi"; 86*4882a593Smuzhiyun reg = <0x41a00 0x200 0x46140 4>; 87*4882a593Smuzhiyun msi-available-ranges = <0 0x100>; 88*4882a593Smuzhiyun interrupts = < 89*4882a593Smuzhiyun 0xf0 0 0 0 90*4882a593Smuzhiyun 0xf1 0 0 0 91*4882a593Smuzhiyun 0xf2 0 0 0 92*4882a593Smuzhiyun 0xf3 0 0 0 93*4882a593Smuzhiyun 0xf4 0 0 0 94*4882a593Smuzhiyun 0xf5 0 0 0 95*4882a593Smuzhiyun 0xf6 0 0 0 96*4882a593Smuzhiyun 0xf7 0 0 0>; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyuntimer@42100 { 100*4882a593Smuzhiyun compatible = "fsl,mpic-global-timer"; 101*4882a593Smuzhiyun reg = <0x42100 0x100 0x42300 4>; 102*4882a593Smuzhiyun interrupts = <4 0 3 0 103*4882a593Smuzhiyun 5 0 3 0 104*4882a593Smuzhiyun 6 0 3 0 105*4882a593Smuzhiyun 7 0 3 0>; 106*4882a593Smuzhiyun}; 107