xref: /OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * P3041 Silicon/SoC Device Tree Source (pre include)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2011 - 2015 Freescale Semiconductor Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met:
8*4882a593Smuzhiyun *     * Redistributions of source code must retain the above copyright
9*4882a593Smuzhiyun *       notice, this list of conditions and the following disclaimer.
10*4882a593Smuzhiyun *     * Redistributions in binary form must reproduce the above copyright
11*4882a593Smuzhiyun *       notice, this list of conditions and the following disclaimer in the
12*4882a593Smuzhiyun *       documentation and/or other materials provided with the distribution.
13*4882a593Smuzhiyun *     * Neither the name of Freescale Semiconductor nor the
14*4882a593Smuzhiyun *       names of its contributors may be used to endorse or promote products
15*4882a593Smuzhiyun *       derived from this software without specific prior written permission.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the
19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software
20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any
21*4882a593Smuzhiyun * later version.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun/dts-v1/;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun/include/ "e500mc_power_isa.dtsi"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun/ {
40*4882a593Smuzhiyun	compatible = "fsl,P3041";
41*4882a593Smuzhiyun	#address-cells = <2>;
42*4882a593Smuzhiyun	#size-cells = <2>;
43*4882a593Smuzhiyun	interrupt-parent = <&mpic>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	aliases {
46*4882a593Smuzhiyun		ccsr = &soc;
47*4882a593Smuzhiyun		dcsr = &dcsr;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		serial0 = &serial0;
50*4882a593Smuzhiyun		serial1 = &serial1;
51*4882a593Smuzhiyun		serial2 = &serial2;
52*4882a593Smuzhiyun		serial3 = &serial3;
53*4882a593Smuzhiyun		pci0 = &pci0;
54*4882a593Smuzhiyun		pci1 = &pci1;
55*4882a593Smuzhiyun		pci2 = &pci2;
56*4882a593Smuzhiyun		pci3 = &pci3;
57*4882a593Smuzhiyun		usb0 = &usb0;
58*4882a593Smuzhiyun		usb1 = &usb1;
59*4882a593Smuzhiyun		dma0 = &dma0;
60*4882a593Smuzhiyun		dma1 = &dma1;
61*4882a593Smuzhiyun		sdhc = &sdhc;
62*4882a593Smuzhiyun		msi0 = &msi0;
63*4882a593Smuzhiyun		msi1 = &msi1;
64*4882a593Smuzhiyun		msi2 = &msi2;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		crypto = &crypto;
67*4882a593Smuzhiyun		sec_jr0 = &sec_jr0;
68*4882a593Smuzhiyun		sec_jr1 = &sec_jr1;
69*4882a593Smuzhiyun		sec_jr2 = &sec_jr2;
70*4882a593Smuzhiyun		sec_jr3 = &sec_jr3;
71*4882a593Smuzhiyun		rtic_a = &rtic_a;
72*4882a593Smuzhiyun		rtic_b = &rtic_b;
73*4882a593Smuzhiyun		rtic_c = &rtic_c;
74*4882a593Smuzhiyun		rtic_d = &rtic_d;
75*4882a593Smuzhiyun		sec_mon = &sec_mon;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		fman0 = &fman0;
78*4882a593Smuzhiyun		ethernet0 = &enet0;
79*4882a593Smuzhiyun		ethernet1 = &enet1;
80*4882a593Smuzhiyun		ethernet2 = &enet2;
81*4882a593Smuzhiyun		ethernet3 = &enet3;
82*4882a593Smuzhiyun		ethernet4 = &enet4;
83*4882a593Smuzhiyun		ethernet5 = &enet5;
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	cpus {
87*4882a593Smuzhiyun		#address-cells = <1>;
88*4882a593Smuzhiyun		#size-cells = <0>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		cpu0: PowerPC,e500mc@0 {
91*4882a593Smuzhiyun			device_type = "cpu";
92*4882a593Smuzhiyun			reg = <0>;
93*4882a593Smuzhiyun			clocks = <&clockgen 1 0>;
94*4882a593Smuzhiyun			next-level-cache = <&L2_0>;
95*4882a593Smuzhiyun			fsl,portid-mapping = <0x80000000>;
96*4882a593Smuzhiyun			L2_0: l2-cache {
97*4882a593Smuzhiyun				next-level-cache = <&cpc>;
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun		cpu1: PowerPC,e500mc@1 {
101*4882a593Smuzhiyun			device_type = "cpu";
102*4882a593Smuzhiyun			reg = <1>;
103*4882a593Smuzhiyun			clocks = <&clockgen 1 1>;
104*4882a593Smuzhiyun			next-level-cache = <&L2_1>;
105*4882a593Smuzhiyun			fsl,portid-mapping = <0x40000000>;
106*4882a593Smuzhiyun			L2_1: l2-cache {
107*4882a593Smuzhiyun				next-level-cache = <&cpc>;
108*4882a593Smuzhiyun			};
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun		cpu2: PowerPC,e500mc@2 {
111*4882a593Smuzhiyun			device_type = "cpu";
112*4882a593Smuzhiyun			reg = <2>;
113*4882a593Smuzhiyun			clocks = <&clockgen 1 2>;
114*4882a593Smuzhiyun			next-level-cache = <&L2_2>;
115*4882a593Smuzhiyun			fsl,portid-mapping = <0x20000000>;
116*4882a593Smuzhiyun			L2_2: l2-cache {
117*4882a593Smuzhiyun				next-level-cache = <&cpc>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun		cpu3: PowerPC,e500mc@3 {
121*4882a593Smuzhiyun			device_type = "cpu";
122*4882a593Smuzhiyun			reg = <3>;
123*4882a593Smuzhiyun			clocks = <&clockgen 1 3>;
124*4882a593Smuzhiyun			next-level-cache = <&L2_3>;
125*4882a593Smuzhiyun			fsl,portid-mapping = <0x10000000>;
126*4882a593Smuzhiyun			L2_3: l2-cache {
127*4882a593Smuzhiyun				next-level-cache = <&cpc>;
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun};
132