1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * P1021/P1012 Silicon/SoC Device Tree Source (post include) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2011-2012 Freescale Semiconductor Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25*4882a593Smuzhiyun * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26*4882a593Smuzhiyun * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27*4882a593Smuzhiyun * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29*4882a593Smuzhiyun * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*4882a593Smuzhiyun * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&lbc { 36*4882a593Smuzhiyun #address-cells = <2>; 37*4882a593Smuzhiyun #size-cells = <1>; 38*4882a593Smuzhiyun compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus"; 39*4882a593Smuzhiyun interrupts = <19 2 0 0>, 40*4882a593Smuzhiyun <16 2 0 0>; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun/* controller at 0x9000 */ 44*4882a593Smuzhiyun&pci0 { 45*4882a593Smuzhiyun compatible = "fsl,mpc8548-pcie"; 46*4882a593Smuzhiyun device_type = "pci"; 47*4882a593Smuzhiyun #size-cells = <2>; 48*4882a593Smuzhiyun #address-cells = <3>; 49*4882a593Smuzhiyun bus-range = <0 255>; 50*4882a593Smuzhiyun clock-frequency = <33333333>; 51*4882a593Smuzhiyun interrupts = <16 2 0 0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun pcie@0 { 54*4882a593Smuzhiyun reg = <0 0 0 0 0>; 55*4882a593Smuzhiyun #interrupt-cells = <1>; 56*4882a593Smuzhiyun #size-cells = <2>; 57*4882a593Smuzhiyun #address-cells = <3>; 58*4882a593Smuzhiyun device_type = "pci"; 59*4882a593Smuzhiyun interrupts = <16 2 0 0>; 60*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 61*4882a593Smuzhiyun interrupt-map = < 62*4882a593Smuzhiyun /* IDSEL 0x0 */ 63*4882a593Smuzhiyun 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 64*4882a593Smuzhiyun 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 65*4882a593Smuzhiyun 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 66*4882a593Smuzhiyun 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 67*4882a593Smuzhiyun >; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun/* controller at 0xa000 */ 72*4882a593Smuzhiyun&pci1 { 73*4882a593Smuzhiyun compatible = "fsl,mpc8548-pcie"; 74*4882a593Smuzhiyun device_type = "pci"; 75*4882a593Smuzhiyun #size-cells = <2>; 76*4882a593Smuzhiyun #address-cells = <3>; 77*4882a593Smuzhiyun bus-range = <0 255>; 78*4882a593Smuzhiyun clock-frequency = <33333333>; 79*4882a593Smuzhiyun interrupts = <16 2 0 0>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun pcie@0 { 82*4882a593Smuzhiyun reg = <0 0 0 0 0>; 83*4882a593Smuzhiyun #interrupt-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <2>; 85*4882a593Smuzhiyun #address-cells = <3>; 86*4882a593Smuzhiyun device_type = "pci"; 87*4882a593Smuzhiyun interrupts = <16 2 0 0>; 88*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun interrupt-map = < 91*4882a593Smuzhiyun /* IDSEL 0x0 */ 92*4882a593Smuzhiyun 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 93*4882a593Smuzhiyun 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 94*4882a593Smuzhiyun 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 95*4882a593Smuzhiyun 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 96*4882a593Smuzhiyun >; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&soc { 101*4882a593Smuzhiyun #address-cells = <1>; 102*4882a593Smuzhiyun #size-cells = <1>; 103*4882a593Smuzhiyun device_type = "soc"; 104*4882a593Smuzhiyun compatible = "fsl,p1021-immr", "simple-bus"; 105*4882a593Smuzhiyun bus-frequency = <0>; // Filled out by uboot. 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun ecm-law@0 { 108*4882a593Smuzhiyun compatible = "fsl,ecm-law"; 109*4882a593Smuzhiyun reg = <0x0 0x1000>; 110*4882a593Smuzhiyun fsl,num-laws = <12>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun ecm@1000 { 114*4882a593Smuzhiyun compatible = "fsl,p1021-ecm", "fsl,ecm"; 115*4882a593Smuzhiyun reg = <0x1000 0x1000>; 116*4882a593Smuzhiyun interrupts = <16 2 0 0>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun memory-controller@2000 { 120*4882a593Smuzhiyun compatible = "fsl,p1021-memory-controller"; 121*4882a593Smuzhiyun reg = <0x2000 0x1000>; 122*4882a593Smuzhiyun interrupts = <16 2 0 0>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun/include/ "pq3-i2c-0.dtsi" 126*4882a593Smuzhiyun/include/ "pq3-i2c-1.dtsi" 127*4882a593Smuzhiyun/include/ "pq3-duart-0.dtsi" 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun/include/ "pq3-espi-0.dtsi" 130*4882a593Smuzhiyun spi@7000 { 131*4882a593Smuzhiyun fsl,espi-num-chipselects = <4>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun/include/ "pq3-gpio-0.dtsi" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun L2: l2-cache-controller@20000 { 137*4882a593Smuzhiyun compatible = "fsl,p1021-l2-cache-controller"; 138*4882a593Smuzhiyun reg = <0x20000 0x1000>; 139*4882a593Smuzhiyun cache-line-size = <32>; // 32 bytes 140*4882a593Smuzhiyun cache-size = <0x40000>; // L2,256K 141*4882a593Smuzhiyun interrupts = <16 2 0 0>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun/include/ "pq3-dma-0.dtsi" 145*4882a593Smuzhiyun/include/ "pq3-usb2-dr-0.dtsi" 146*4882a593Smuzhiyun usb@22000 { 147*4882a593Smuzhiyun compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun/include/ "pq3-esdhc-0.dtsi" 151*4882a593Smuzhiyun sdhc@2e000 { 152*4882a593Smuzhiyun sdhci,auto-cmd12; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun/include/ "pq3-sec3.3-0.dtsi" 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun/include/ "pq3-mpic.dtsi" 158*4882a593Smuzhiyun/include/ "pq3-mpic-timer-B.dtsi" 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun/include/ "pq3-etsec2-0.dtsi" 161*4882a593Smuzhiyun enet0: enet0_grp2: ethernet@b0000 { 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun/include/ "pq3-etsec2-1.dtsi" 165*4882a593Smuzhiyun enet1: enet1_grp2: ethernet@b1000 { 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun/include/ "pq3-etsec2-2.dtsi" 169*4882a593Smuzhiyun enet2: enet2_grp2: ethernet@b2000 { 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun global-utilities@e0000 { 173*4882a593Smuzhiyun compatible = "fsl,p1021-guts"; 174*4882a593Smuzhiyun reg = <0xe0000 0x1000>; 175*4882a593Smuzhiyun fsl,has-rstcr; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&qe { 180*4882a593Smuzhiyun #address-cells = <1>; 181*4882a593Smuzhiyun #size-cells = <1>; 182*4882a593Smuzhiyun device_type = "qe"; 183*4882a593Smuzhiyun compatible = "fsl,qe"; 184*4882a593Smuzhiyun fsl,qe-num-riscs = <1>; 185*4882a593Smuzhiyun fsl,qe-num-snums = <28>; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun qeic: interrupt-controller@80 { 188*4882a593Smuzhiyun interrupt-controller; 189*4882a593Smuzhiyun compatible = "fsl,qe-ic"; 190*4882a593Smuzhiyun #address-cells = <0>; 191*4882a593Smuzhiyun #interrupt-cells = <1>; 192*4882a593Smuzhiyun reg = <0x80 0x80>; 193*4882a593Smuzhiyun interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun ucc@2000 { 197*4882a593Smuzhiyun cell-index = <1>; 198*4882a593Smuzhiyun reg = <0x2000 0x200>; 199*4882a593Smuzhiyun interrupts = <32>; 200*4882a593Smuzhiyun interrupt-parent = <&qeic>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun mdio@2120 { 204*4882a593Smuzhiyun #address-cells = <1>; 205*4882a593Smuzhiyun #size-cells = <0>; 206*4882a593Smuzhiyun reg = <0x2120 0x18>; 207*4882a593Smuzhiyun compatible = "fsl,ucc-mdio"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun ucc@2400 { 211*4882a593Smuzhiyun cell-index = <5>; 212*4882a593Smuzhiyun reg = <0x2400 0x200>; 213*4882a593Smuzhiyun interrupts = <40>; 214*4882a593Smuzhiyun interrupt-parent = <&qeic>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun ucc@2600 { 218*4882a593Smuzhiyun cell-index = <7>; 219*4882a593Smuzhiyun reg = <0x2600 0x200>; 220*4882a593Smuzhiyun interrupts = <42>; 221*4882a593Smuzhiyun interrupt-parent = <&qeic>; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun ucc@2200 { 225*4882a593Smuzhiyun cell-index = <3>; 226*4882a593Smuzhiyun reg = <0x2200 0x200>; 227*4882a593Smuzhiyun interrupts = <34>; 228*4882a593Smuzhiyun interrupt-parent = <&qeic>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun muram@10000 { 232*4882a593Smuzhiyun #address-cells = <1>; 233*4882a593Smuzhiyun #size-cells = <1>; 234*4882a593Smuzhiyun compatible = "fsl,qe-muram", "fsl,cpm-muram"; 235*4882a593Smuzhiyun ranges = <0x0 0x10000 0x6000>; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun data-only@0 { 238*4882a593Smuzhiyun compatible = "fsl,qe-muram-data", 239*4882a593Smuzhiyun "fsl,cpm-muram-data"; 240*4882a593Smuzhiyun reg = <0x0 0x6000>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun/include/ "pq3-etsec2-grp2-0.dtsi" 246*4882a593Smuzhiyun/include/ "pq3-etsec2-grp2-1.dtsi" 247*4882a593Smuzhiyun/include/ "pq3-etsec2-grp2-2.dtsi" 248