1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8641 Silicon/SoC Device Tree Source (post include) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&lbc { 9*4882a593Smuzhiyun #address-cells = <2>; 10*4882a593Smuzhiyun #size-cells = <1>; 11*4882a593Smuzhiyun compatible = "fsl,mpc8641-localbus", "simple-bus"; 12*4882a593Smuzhiyun interrupts = <19 2 0 0>; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&soc { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <1>; 18*4882a593Smuzhiyun device_type = "soc"; 19*4882a593Smuzhiyun compatible = "fsl,mpc8641-soc", "simple-bus"; 20*4882a593Smuzhiyun bus-frequency = <0>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mcm-law@0 { 23*4882a593Smuzhiyun compatible = "fsl,mcm-law"; 24*4882a593Smuzhiyun reg = <0x0 0x1000>; 25*4882a593Smuzhiyun fsl,num-laws = <10>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun mcm@1000 { 29*4882a593Smuzhiyun compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 30*4882a593Smuzhiyun reg = <0x1000 0x1000>; 31*4882a593Smuzhiyun interrupts = <17 2 0 0>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun/include/ "pq3-i2c-0.dtsi" 35*4882a593Smuzhiyun/include/ "pq3-i2c-1.dtsi" 36*4882a593Smuzhiyun/include/ "pq3-duart-0.dtsi" 37*4882a593Smuzhiyun serial@4600 { 38*4882a593Smuzhiyun interrupts = <28 2 0 0>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun/include/ "pq3-dma-0.dtsi" 41*4882a593Smuzhiyun dma@21300 { 42*4882a593Smuzhiyun compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun dma-channel@0 { 45*4882a593Smuzhiyun compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun dma-channel@80 { 48*4882a593Smuzhiyun compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun dma-channel@100 { 51*4882a593Smuzhiyun compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun dma-channel@180 { 54*4882a593Smuzhiyun compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun/include/ "pq3-etsec1-0.dtsi" 58*4882a593Smuzhiyun ethernet@24000 { 59*4882a593Smuzhiyun model = "TSEC"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun/include/ "pq3-etsec1-1.dtsi" 62*4882a593Smuzhiyun ethernet@25000 { 63*4882a593Smuzhiyun model = "TSEC"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun/include/ "pq3-etsec1-2.dtsi" 66*4882a593Smuzhiyun ethernet@26000 { 67*4882a593Smuzhiyun model = "TSEC"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun/include/ "pq3-etsec1-3.dtsi" 70*4882a593Smuzhiyun ethernet@27000 { 71*4882a593Smuzhiyun model = "TSEC"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun/include/ "qoriq-mpic.dtsi" 75*4882a593Smuzhiyun msi@41600 { 76*4882a593Smuzhiyun compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun msi@41800 { 79*4882a593Smuzhiyun compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun msi@41a00 { 82*4882a593Smuzhiyun compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun global-utilities@e0000 { 86*4882a593Smuzhiyun compatible = "fsl,mpc8641-guts"; 87*4882a593Smuzhiyun reg = <0xe0000 0x1000>; 88*4882a593Smuzhiyun fsl,has-rstcr; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&pci0 { 93*4882a593Smuzhiyun compatible = "fsl,mpc8641-pcie"; 94*4882a593Smuzhiyun device_type = "pci"; 95*4882a593Smuzhiyun #interrupt-cells = <1>; 96*4882a593Smuzhiyun #size-cells = <2>; 97*4882a593Smuzhiyun #address-cells = <3>; 98*4882a593Smuzhiyun bus-range = <0x0 0xff>; 99*4882a593Smuzhiyun clock-frequency = <100000000>; 100*4882a593Smuzhiyun interrupts = <24 2 0 0>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun pcie@0 { 103*4882a593Smuzhiyun reg = <0 0 0 0 0>; 104*4882a593Smuzhiyun #interrupt-cells = <1>; 105*4882a593Smuzhiyun #size-cells = <2>; 106*4882a593Smuzhiyun #address-cells = <3>; 107*4882a593Smuzhiyun device_type = "pci"; 108*4882a593Smuzhiyun interrupts = <24 2 0 0>; 109*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 110*4882a593Smuzhiyun interrupt-map = < 111*4882a593Smuzhiyun 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 112*4882a593Smuzhiyun 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 113*4882a593Smuzhiyun 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 114*4882a593Smuzhiyun 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 115*4882a593Smuzhiyun >; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&pci1 { 120*4882a593Smuzhiyun compatible = "fsl,mpc8641-pcie"; 121*4882a593Smuzhiyun device_type = "pci"; 122*4882a593Smuzhiyun #interrupt-cells = <1>; 123*4882a593Smuzhiyun #size-cells = <2>; 124*4882a593Smuzhiyun #address-cells = <3>; 125*4882a593Smuzhiyun bus-range = <0x0 0xff>; 126*4882a593Smuzhiyun clock-frequency = <100000000>; 127*4882a593Smuzhiyun interrupts = <25 2 0 0>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun pcie@0 { 130*4882a593Smuzhiyun reg = <0 0 0 0 0>; 131*4882a593Smuzhiyun #interrupt-cells = <1>; 132*4882a593Smuzhiyun #size-cells = <2>; 133*4882a593Smuzhiyun #address-cells = <3>; 134*4882a593Smuzhiyun device_type = "pci"; 135*4882a593Smuzhiyun interrupts = <25 2 0 0>; 136*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 137*4882a593Smuzhiyun interrupt-map = < 138*4882a593Smuzhiyun 0x0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 139*4882a593Smuzhiyun 0x0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 140*4882a593Smuzhiyun 0x0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 141*4882a593Smuzhiyun 0x0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 142*4882a593Smuzhiyun >; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun}; 145