1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MPC8544 DS Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007, 2008 Freescale Semiconductor Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/include/ "mpc8544si-pre.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "MPC8544DS"; 12*4882a593Smuzhiyun compatible = "MPC8544DS", "MPC85xxDS"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0 0 0 0>; // Filled by U-Boot 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun board_lbc: lbc: localbus@e0005000 { 20*4882a593Smuzhiyun reg = <0 0xe0005000 0 0x1000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0xff800000 0x800000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun board_soc: soc: soc8544@e0000000 { 26*4882a593Smuzhiyun ranges = <0x0 0x0 0xe0000000 0x100000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun pci0: pci@e0008000 { 30*4882a593Smuzhiyun reg = <0 0xe0008000 0 0x1000>; 31*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 32*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>; 33*4882a593Smuzhiyun clock-frequency = <66666666>; 34*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 35*4882a593Smuzhiyun interrupt-map = < 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* IDSEL 0x11 J17 Slot 1 */ 38*4882a593Smuzhiyun 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0 39*4882a593Smuzhiyun 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0 40*4882a593Smuzhiyun 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0 41*4882a593Smuzhiyun 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* IDSEL 0x12 J16 Slot 2 */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0 46*4882a593Smuzhiyun 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0 47*4882a593Smuzhiyun 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0 48*4882a593Smuzhiyun 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun pci1: pcie@e0009000 { 52*4882a593Smuzhiyun reg = <0x0 0xe0009000 0x0 0x1000>; 53*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 54*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>; 55*4882a593Smuzhiyun pcie@0 { 56*4882a593Smuzhiyun ranges = <0x2000000 0x0 0x80000000 57*4882a593Smuzhiyun 0x2000000 0x0 0x80000000 58*4882a593Smuzhiyun 0x0 0x20000000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 0x1000000 0x0 0x0 61*4882a593Smuzhiyun 0x1000000 0x0 0x0 62*4882a593Smuzhiyun 0x0 0x10000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun pci2: pcie@e000a000 { 67*4882a593Smuzhiyun reg = <0x0 0xe000a000 0x0 0x1000>; 68*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 69*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>; 70*4882a593Smuzhiyun pcie@0 { 71*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xa0000000 72*4882a593Smuzhiyun 0x2000000 0x0 0xa0000000 73*4882a593Smuzhiyun 0x0 0x10000000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun 0x1000000 0x0 0x0 76*4882a593Smuzhiyun 0x1000000 0x0 0x0 77*4882a593Smuzhiyun 0x0 0x10000>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun board_pci3: pci3: pcie@e000b000 { 82*4882a593Smuzhiyun reg = <0x0 0xe000b000 0x0 0x1000>; 83*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000 84*4882a593Smuzhiyun 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>; 85*4882a593Smuzhiyun pcie@0 { 86*4882a593Smuzhiyun ranges = <0x2000000 0x0 0xb0000000 87*4882a593Smuzhiyun 0x2000000 0x0 0xb0000000 88*4882a593Smuzhiyun 0x0 0x100000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 0x1000000 0x0 0x0 91*4882a593Smuzhiyun 0x1000000 0x0 0x0 92*4882a593Smuzhiyun 0x0 0x100000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun/* 98*4882a593Smuzhiyun * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings 99*4882a593Smuzhiyun * for interrupt-map & interrupt-map-mask 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun/include/ "mpc8544si-post.dtsi" 103*4882a593Smuzhiyun/include/ "mpc8544ds.dtsi" 104