1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * B4420 Silicon/SoC Device Tree Source (pre include) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2012 - 2015 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 7*4882a593Smuzhiyun * modification, are permitted provided that the following conditions are met: 8*4882a593Smuzhiyun * * Redistributions of source code must retain the above copyright 9*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 10*4882a593Smuzhiyun * * Redistributions in binary form must reproduce the above copyright 11*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in the 12*4882a593Smuzhiyun * documentation and/or other materials provided with the distribution. 13*4882a593Smuzhiyun * * Neither the name of Freescale Semiconductor nor the 14*4882a593Smuzhiyun * names of its contributors may be used to endorse or promote products 15*4882a593Smuzhiyun * derived from this software without specific prior written permission. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * ALTERNATIVELY, this software may be distributed under the terms of the 19*4882a593Smuzhiyun * GNU General Public License ("GPL") as published by the Free Software 20*4882a593Smuzhiyun * Foundation, either version 2 of that License or (at your option) any 21*4882a593Smuzhiyun * later version. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * This software is provided by Freescale Semiconductor "as is" and any 24*4882a593Smuzhiyun * express or implied warranties, including, but not limited to, the implied 25*4882a593Smuzhiyun * warranties of merchantability and fitness for a particular purpose are 26*4882a593Smuzhiyun * disclaimed. In no event shall Freescale Semiconductor be liable for any 27*4882a593Smuzhiyun * direct, indirect, incidental, special, exemplary, or consequential damages 28*4882a593Smuzhiyun * (including, but not limited to, procurement of substitute goods or services; 29*4882a593Smuzhiyun * loss of use, data, or profits; or business interruption) however caused and 30*4882a593Smuzhiyun * on any theory of liability, whether in contract, strict liability, or tort 31*4882a593Smuzhiyun * (including negligence or otherwise) arising in any way out of the use of 32*4882a593Smuzhiyun * this software, even if advised of the possibility of such damage. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun/dts-v1/; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun/include/ "e6500_power_isa.dtsi" 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun/ { 40*4882a593Smuzhiyun compatible = "fsl,B4420"; 41*4882a593Smuzhiyun #address-cells = <2>; 42*4882a593Smuzhiyun #size-cells = <2>; 43*4882a593Smuzhiyun interrupt-parent = <&mpic>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun aliases { 46*4882a593Smuzhiyun ccsr = &soc; 47*4882a593Smuzhiyun dcsr = &dcsr; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun serial0 = &serial0; 50*4882a593Smuzhiyun serial1 = &serial1; 51*4882a593Smuzhiyun serial2 = &serial2; 52*4882a593Smuzhiyun serial3 = &serial3; 53*4882a593Smuzhiyun pci0 = &pci0; 54*4882a593Smuzhiyun usb0 = &usb0; 55*4882a593Smuzhiyun dma0 = &dma0; 56*4882a593Smuzhiyun dma1 = &dma1; 57*4882a593Smuzhiyun sdhc = &sdhc; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun fman0 = &fman0; 60*4882a593Smuzhiyun ethernet0 = &enet0; 61*4882a593Smuzhiyun ethernet1 = &enet1; 62*4882a593Smuzhiyun ethernet2 = &enet2; 63*4882a593Smuzhiyun ethernet3 = &enet3; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun cpus { 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <0>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun cpu0: PowerPC,e6500@0 { 71*4882a593Smuzhiyun device_type = "cpu"; 72*4882a593Smuzhiyun reg = <0 1>; 73*4882a593Smuzhiyun clocks = <&clockgen 1 0>; 74*4882a593Smuzhiyun next-level-cache = <&L2_1>; 75*4882a593Smuzhiyun fsl,portid-mapping = <0x80000000>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun cpu1: PowerPC,e6500@2 { 78*4882a593Smuzhiyun device_type = "cpu"; 79*4882a593Smuzhiyun reg = <2 3>; 80*4882a593Smuzhiyun clocks = <&clockgen 1 0>; 81*4882a593Smuzhiyun next-level-cache = <&L2_1>; 82*4882a593Smuzhiyun fsl,portid-mapping = <0x80000000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun}; 86