1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * CM5200 board Device Tree Source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Semihalf 6*4882a593Smuzhiyun * Marian Balakowicz <m8@semihalf.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/include/ "mpc5200b.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&gpt0 { fsl,has-wdt; }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "schindler,cm5200"; 15*4882a593Smuzhiyun compatible = "schindler,cm5200"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun soc5200@f0000000 { 18*4882a593Smuzhiyun can@900 { 19*4882a593Smuzhiyun status = "disabled"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun can@980 { 23*4882a593Smuzhiyun status = "disabled"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun psc@2000 { // PSC1 27*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun psc@2200 { // PSC2 31*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun psc@2400 { // PSC3 35*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun psc@2600 { // PSC4 39*4882a593Smuzhiyun status = "disabled"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun psc@2800 { // PSC5 43*4882a593Smuzhiyun status = "disabled"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun psc@2c00 { // PSC6 47*4882a593Smuzhiyun compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun ethernet@3000 { 51*4882a593Smuzhiyun phy-handle = <&phy0>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun mdio@3000 { 55*4882a593Smuzhiyun phy0: ethernet-phy@0 { 56*4882a593Smuzhiyun reg = <0>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ata@3a00 { 61*4882a593Smuzhiyun status = "disabled"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun i2c@3d00 { 65*4882a593Smuzhiyun status = "disabled"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun pci@f0000d00 { 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun localbus { 75*4882a593Smuzhiyun // 16-bit flash device at LocalPlus Bus CS0 76*4882a593Smuzhiyun flash@0,0 { 77*4882a593Smuzhiyun compatible = "cfi-flash"; 78*4882a593Smuzhiyun reg = <0 0 0x2000000>; 79*4882a593Smuzhiyun bank-width = <2>; 80*4882a593Smuzhiyun device-width = <2>; 81*4882a593Smuzhiyun #size-cells = <1>; 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun}; 86