1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * CPM serial console support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2007 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * Author: Scott Wood <scottwood@freescale.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * It is assumed that the firmware (or the platform file) has already set
9*4882a593Smuzhiyun * up the port.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "types.h"
13*4882a593Smuzhiyun #include "io.h"
14*4882a593Smuzhiyun #include "ops.h"
15*4882a593Smuzhiyun #include "page.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct cpm_scc {
18*4882a593Smuzhiyun u32 gsmrl;
19*4882a593Smuzhiyun u32 gsmrh;
20*4882a593Smuzhiyun u16 psmr;
21*4882a593Smuzhiyun u8 res1[2];
22*4882a593Smuzhiyun u16 todr;
23*4882a593Smuzhiyun u16 dsr;
24*4882a593Smuzhiyun u16 scce;
25*4882a593Smuzhiyun u8 res2[2];
26*4882a593Smuzhiyun u16 sccm;
27*4882a593Smuzhiyun u8 res3;
28*4882a593Smuzhiyun u8 sccs;
29*4882a593Smuzhiyun u8 res4[8];
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun struct cpm_smc {
33*4882a593Smuzhiyun u8 res1[2];
34*4882a593Smuzhiyun u16 smcmr;
35*4882a593Smuzhiyun u8 res2[2];
36*4882a593Smuzhiyun u8 smce;
37*4882a593Smuzhiyun u8 res3[3];
38*4882a593Smuzhiyun u8 smcm;
39*4882a593Smuzhiyun u8 res4[5];
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct cpm_param {
43*4882a593Smuzhiyun u16 rbase;
44*4882a593Smuzhiyun u16 tbase;
45*4882a593Smuzhiyun u8 rfcr;
46*4882a593Smuzhiyun u8 tfcr;
47*4882a593Smuzhiyun u16 mrblr;
48*4882a593Smuzhiyun u32 rstate;
49*4882a593Smuzhiyun u8 res1[4];
50*4882a593Smuzhiyun u16 rbptr;
51*4882a593Smuzhiyun u8 res2[6];
52*4882a593Smuzhiyun u32 tstate;
53*4882a593Smuzhiyun u8 res3[4];
54*4882a593Smuzhiyun u16 tbptr;
55*4882a593Smuzhiyun u8 res4[6];
56*4882a593Smuzhiyun u16 maxidl;
57*4882a593Smuzhiyun u16 idlc;
58*4882a593Smuzhiyun u16 brkln;
59*4882a593Smuzhiyun u16 brkec;
60*4882a593Smuzhiyun u16 brkcr;
61*4882a593Smuzhiyun u16 rmask;
62*4882a593Smuzhiyun u8 res5[4];
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct cpm_bd {
66*4882a593Smuzhiyun u16 sc; /* Status and Control */
67*4882a593Smuzhiyun u16 len; /* Data length in buffer */
68*4882a593Smuzhiyun u8 *addr; /* Buffer address in host memory */
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static void *cpcr;
72*4882a593Smuzhiyun static struct cpm_param *param;
73*4882a593Smuzhiyun static struct cpm_smc *smc;
74*4882a593Smuzhiyun static struct cpm_scc *scc;
75*4882a593Smuzhiyun static struct cpm_bd *tbdf, *rbdf;
76*4882a593Smuzhiyun static u32 cpm_cmd;
77*4882a593Smuzhiyun static void *cbd_addr;
78*4882a593Smuzhiyun static u32 cbd_offset;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static void (*do_cmd)(int op);
81*4882a593Smuzhiyun static void (*enable_port)(void);
82*4882a593Smuzhiyun static void (*disable_port)(void);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define CPM_CMD_STOP_TX 4
85*4882a593Smuzhiyun #define CPM_CMD_RESTART_TX 6
86*4882a593Smuzhiyun #define CPM_CMD_INIT_RX_TX 0
87*4882a593Smuzhiyun
cpm1_cmd(int op)88*4882a593Smuzhiyun static void cpm1_cmd(int op)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun while (in_be16(cpcr) & 1)
91*4882a593Smuzhiyun ;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun out_be16(cpcr, (op << 8) | cpm_cmd | 1);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun while (in_be16(cpcr) & 1)
96*4882a593Smuzhiyun ;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
cpm2_cmd(int op)99*4882a593Smuzhiyun static void cpm2_cmd(int op)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun while (in_be32(cpcr) & 0x10000)
102*4882a593Smuzhiyun ;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun out_be32(cpcr, op | cpm_cmd | 0x10000);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun while (in_be32(cpcr) & 0x10000)
107*4882a593Smuzhiyun ;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
smc_disable_port(void)110*4882a593Smuzhiyun static void smc_disable_port(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun do_cmd(CPM_CMD_STOP_TX);
113*4882a593Smuzhiyun out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
scc_disable_port(void)116*4882a593Smuzhiyun static void scc_disable_port(void)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun do_cmd(CPM_CMD_STOP_TX);
119*4882a593Smuzhiyun out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
smc_enable_port(void)122*4882a593Smuzhiyun static void smc_enable_port(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
125*4882a593Smuzhiyun do_cmd(CPM_CMD_RESTART_TX);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
scc_enable_port(void)128*4882a593Smuzhiyun static void scc_enable_port(void)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
131*4882a593Smuzhiyun do_cmd(CPM_CMD_RESTART_TX);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
cpm_serial_open(void)134*4882a593Smuzhiyun static int cpm_serial_open(void)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun disable_port();
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun out_8(¶m->rfcr, 0x10);
139*4882a593Smuzhiyun out_8(¶m->tfcr, 0x10);
140*4882a593Smuzhiyun out_be16(¶m->mrblr, 1);
141*4882a593Smuzhiyun out_be16(¶m->maxidl, 0);
142*4882a593Smuzhiyun out_be16(¶m->brkec, 0);
143*4882a593Smuzhiyun out_be16(¶m->brkln, 0);
144*4882a593Smuzhiyun out_be16(¶m->brkcr, 0);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun rbdf = cbd_addr;
147*4882a593Smuzhiyun rbdf->addr = (u8 *)rbdf - 1;
148*4882a593Smuzhiyun rbdf->sc = 0xa000;
149*4882a593Smuzhiyun rbdf->len = 1;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun tbdf = rbdf + 1;
152*4882a593Smuzhiyun tbdf->addr = (u8 *)rbdf - 2;
153*4882a593Smuzhiyun tbdf->sc = 0x2000;
154*4882a593Smuzhiyun tbdf->len = 1;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun sync();
157*4882a593Smuzhiyun out_be16(¶m->rbase, cbd_offset);
158*4882a593Smuzhiyun out_be16(¶m->tbase, cbd_offset + sizeof(struct cpm_bd));
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun do_cmd(CPM_CMD_INIT_RX_TX);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun enable_port();
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
cpm_serial_putc(unsigned char c)166*4882a593Smuzhiyun static void cpm_serial_putc(unsigned char c)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun while (tbdf->sc & 0x8000)
169*4882a593Smuzhiyun barrier();
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun sync();
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun tbdf->addr[0] = c;
174*4882a593Smuzhiyun eieio();
175*4882a593Smuzhiyun tbdf->sc |= 0x8000;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
cpm_serial_tstc(void)178*4882a593Smuzhiyun static unsigned char cpm_serial_tstc(void)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun barrier();
181*4882a593Smuzhiyun return !(rbdf->sc & 0x8000);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
cpm_serial_getc(void)184*4882a593Smuzhiyun static unsigned char cpm_serial_getc(void)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun unsigned char c;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun while (!cpm_serial_tstc())
189*4882a593Smuzhiyun ;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun sync();
192*4882a593Smuzhiyun c = rbdf->addr[0];
193*4882a593Smuzhiyun eieio();
194*4882a593Smuzhiyun rbdf->sc |= 0x8000;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return c;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
cpm_console_init(void * devp,struct serial_console_data * scdp)199*4882a593Smuzhiyun int cpm_console_init(void *devp, struct serial_console_data *scdp)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun void *vreg[2];
202*4882a593Smuzhiyun u32 reg[2];
203*4882a593Smuzhiyun int is_smc = 0, is_cpm2 = 0;
204*4882a593Smuzhiyun void *parent, *muram;
205*4882a593Smuzhiyun void *muram_addr;
206*4882a593Smuzhiyun unsigned long muram_offset, muram_size;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
209*4882a593Smuzhiyun is_smc = 1;
210*4882a593Smuzhiyun } else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
211*4882a593Smuzhiyun is_cpm2 = 1;
212*4882a593Smuzhiyun } else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
213*4882a593Smuzhiyun is_cpm2 = 1;
214*4882a593Smuzhiyun is_smc = 1;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if (is_smc) {
218*4882a593Smuzhiyun enable_port = smc_enable_port;
219*4882a593Smuzhiyun disable_port = smc_disable_port;
220*4882a593Smuzhiyun } else {
221*4882a593Smuzhiyun enable_port = scc_enable_port;
222*4882a593Smuzhiyun disable_port = scc_disable_port;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (is_cpm2)
226*4882a593Smuzhiyun do_cmd = cpm2_cmd;
227*4882a593Smuzhiyun else
228*4882a593Smuzhiyun do_cmd = cpm1_cmd;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
231*4882a593Smuzhiyun return -1;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (dt_get_virtual_reg(devp, vreg, 2) < 2)
234*4882a593Smuzhiyun return -1;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (is_smc)
237*4882a593Smuzhiyun smc = vreg[0];
238*4882a593Smuzhiyun else
239*4882a593Smuzhiyun scc = vreg[0];
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun param = vreg[1];
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun parent = get_parent(devp);
244*4882a593Smuzhiyun if (!parent)
245*4882a593Smuzhiyun return -1;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
248*4882a593Smuzhiyun return -1;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun muram = finddevice("/soc/cpm/muram/data");
251*4882a593Smuzhiyun if (!muram)
252*4882a593Smuzhiyun return -1;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* For bootwrapper-compatible device trees, we assume that the first
255*4882a593Smuzhiyun * entry has at least 128 bytes, and that #address-cells/#data-cells
256*4882a593Smuzhiyun * is one for both parent and child.
257*4882a593Smuzhiyun */
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
260*4882a593Smuzhiyun return -1;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (getprop(muram, "reg", reg, 8) < 8)
263*4882a593Smuzhiyun return -1;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun muram_offset = reg[0];
266*4882a593Smuzhiyun muram_size = reg[1];
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /* Store the buffer descriptors at the end of the first muram chunk.
269*4882a593Smuzhiyun * For SMC ports on CPM2-based platforms, relocate the parameter RAM
270*4882a593Smuzhiyun * just before the buffer descriptors.
271*4882a593Smuzhiyun */
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if (is_cpm2 && is_smc) {
276*4882a593Smuzhiyun u16 *smc_base = (u16 *)param;
277*4882a593Smuzhiyun u16 pram_offset;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun pram_offset = cbd_offset - 64;
280*4882a593Smuzhiyun pram_offset = _ALIGN_DOWN(pram_offset, 64);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun disable_port();
283*4882a593Smuzhiyun out_be16(smc_base, pram_offset);
284*4882a593Smuzhiyun param = muram_addr - muram_offset + pram_offset;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun cbd_addr = muram_addr - muram_offset + cbd_offset;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun scdp->open = cpm_serial_open;
290*4882a593Smuzhiyun scdp->putc = cpm_serial_putc;
291*4882a593Smuzhiyun scdp->getc = cpm_serial_getc;
292*4882a593Smuzhiyun scdp->tstc = cpm_serial_tstc;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296