1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Floating-point emulation code
6*4882a593Smuzhiyun * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun /*
9*4882a593Smuzhiyun * linux/arch/math-emu/driver.c.c
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * decodes and dispatches unimplemented FPU instructions
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Copyright (C) 1999, 2000 Philipp Rumpf <prumpf@tux.org>
14*4882a593Smuzhiyun * Copyright (C) 2001 Hewlett-Packard <bame@debian.org>
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/sched/signal.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "float.h"
20*4882a593Smuzhiyun #include "math-emu.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define fptpos 31
24*4882a593Smuzhiyun #define fpr1pos 10
25*4882a593Smuzhiyun #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define FPUDEBUG 0
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Format of the floating-point exception registers. */
30*4882a593Smuzhiyun struct exc_reg {
31*4882a593Smuzhiyun unsigned int exception : 6;
32*4882a593Smuzhiyun unsigned int ei : 26;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Macros for grabbing bits of the instruction format from the 'ei'
36*4882a593Smuzhiyun field above. */
37*4882a593Smuzhiyun /* Major opcode 0c and 0e */
38*4882a593Smuzhiyun #define FP0CE_UID(i) (((i) >> 6) & 3)
39*4882a593Smuzhiyun #define FP0CE_CLASS(i) (((i) >> 9) & 3)
40*4882a593Smuzhiyun #define FP0CE_SUBOP(i) (((i) >> 13) & 7)
41*4882a593Smuzhiyun #define FP0CE_SUBOP1(i) (((i) >> 15) & 7) /* Class 1 subopcode */
42*4882a593Smuzhiyun #define FP0C_FORMAT(i) (((i) >> 11) & 3)
43*4882a593Smuzhiyun #define FP0E_FORMAT(i) (((i) >> 11) & 1)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Major opcode 0c, uid 2 (performance monitoring) */
46*4882a593Smuzhiyun #define FPPM_SUBOP(i) (((i) >> 9) & 0x1f)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Major opcode 2e (fused operations). */
49*4882a593Smuzhiyun #define FP2E_SUBOP(i) (((i) >> 5) & 1)
50*4882a593Smuzhiyun #define FP2E_FORMAT(i) (((i) >> 11) & 1)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Major opcode 26 (FMPYSUB) */
53*4882a593Smuzhiyun /* Major opcode 06 (FMPYADD) */
54*4882a593Smuzhiyun #define FPx6_FORMAT(i) ((i) & 0x1f)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Flags and enable bits of the status word. */
57*4882a593Smuzhiyun #define FPSW_FLAGS(w) ((w) >> 27)
58*4882a593Smuzhiyun #define FPSW_ENABLE(w) ((w) & 0x1f)
59*4882a593Smuzhiyun #define FPSW_V (1<<4)
60*4882a593Smuzhiyun #define FPSW_Z (1<<3)
61*4882a593Smuzhiyun #define FPSW_O (1<<2)
62*4882a593Smuzhiyun #define FPSW_U (1<<1)
63*4882a593Smuzhiyun #define FPSW_I (1<<0)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Handle a floating point exception. Return zero if the faulting
66*4882a593Smuzhiyun instruction can be completed successfully. */
67*4882a593Smuzhiyun int
handle_fpe(struct pt_regs * regs)68*4882a593Smuzhiyun handle_fpe(struct pt_regs *regs)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun extern void printbinary(unsigned long x, int nbits);
71*4882a593Smuzhiyun unsigned int orig_sw, sw;
72*4882a593Smuzhiyun int signalcode;
73*4882a593Smuzhiyun /* need an intermediate copy of float regs because FPU emulation
74*4882a593Smuzhiyun * code expects an artificial last entry which contains zero
75*4882a593Smuzhiyun *
76*4882a593Smuzhiyun * also, the passed in fr registers contain one word that defines
77*4882a593Smuzhiyun * the fpu type. the fpu type information is constructed
78*4882a593Smuzhiyun * inside the emulation code
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun __u64 frcopy[36];
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun memcpy(frcopy, regs->fr, sizeof regs->fr);
83*4882a593Smuzhiyun frcopy[32] = 0;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun memcpy(&orig_sw, frcopy, sizeof(orig_sw));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (FPUDEBUG) {
88*4882a593Smuzhiyun printk(KERN_DEBUG "FP VZOUICxxxxCQCQCQCQCQCRMxxTDVZOUI ->\n ");
89*4882a593Smuzhiyun printbinary(orig_sw, 32);
90*4882a593Smuzhiyun printk(KERN_DEBUG "\n");
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun signalcode = decode_fpu(frcopy, 0x666);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Status word = FR0L. */
96*4882a593Smuzhiyun memcpy(&sw, frcopy, sizeof(sw));
97*4882a593Smuzhiyun if (FPUDEBUG) {
98*4882a593Smuzhiyun printk(KERN_DEBUG "VZOUICxxxxCQCQCQCQCQCRMxxTDVZOUI decode_fpu returns %d|0x%x\n",
99*4882a593Smuzhiyun signalcode >> 24, signalcode & 0xffffff);
100*4882a593Smuzhiyun printbinary(sw, 32);
101*4882a593Smuzhiyun printk(KERN_DEBUG "\n");
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun memcpy(regs->fr, frcopy, sizeof regs->fr);
105*4882a593Smuzhiyun if (signalcode != 0) {
106*4882a593Smuzhiyun force_sig_fault(signalcode >> 24, signalcode & 0xffffff,
107*4882a593Smuzhiyun (void __user *) regs->iaoq[0]);
108*4882a593Smuzhiyun return -1;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return signalcode ? -1 : 0;
112*4882a593Smuzhiyun }
113