1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * eisa_eeprom.h - provide support for EISA adapters in PA-RISC machines 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2001, 2002 Daniel Engstrom <5116@telia.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef ASM_EISA_EEPROM_H 9*4882a593Smuzhiyun #define ASM_EISA_EEPROM_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun extern void __iomem *eisa_eeprom_addr; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define HPEE_MAX_LENGTH 0x2000 /* maximum eeprom length */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define HPEE_SLOT_INFO(slot) (20+(48*slot)) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct eeprom_header 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun u_int32_t num_writes; /* number of writes */ 21*4882a593Smuzhiyun u_int8_t flags; /* flags, usage? */ 22*4882a593Smuzhiyun u_int8_t ver_maj; 23*4882a593Smuzhiyun u_int8_t ver_min; 24*4882a593Smuzhiyun u_int8_t num_slots; /* number of EISA slots in system */ 25*4882a593Smuzhiyun u_int16_t csum; /* checksum, I don't know how to calculate this */ 26*4882a593Smuzhiyun u_int8_t pad[10]; 27*4882a593Smuzhiyun } __attribute__ ((packed)); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct eeprom_eisa_slot_info 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun u_int32_t eisa_slot_id; 33*4882a593Smuzhiyun u_int32_t config_data_offset; 34*4882a593Smuzhiyun u_int32_t num_writes; 35*4882a593Smuzhiyun u_int16_t csum; 36*4882a593Smuzhiyun u_int16_t num_functions; 37*4882a593Smuzhiyun u_int16_t config_data_length; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* bits 0..3 are the duplicate slot id */ 40*4882a593Smuzhiyun #define HPEE_SLOT_INFO_EMBEDDED 0x10 41*4882a593Smuzhiyun #define HPEE_SLOT_INFO_VIRTUAL 0x20 42*4882a593Smuzhiyun #define HPEE_SLOT_INFO_NO_READID 0x40 43*4882a593Smuzhiyun #define HPEE_SLOT_INFO_DUPLICATE 0x80 44*4882a593Smuzhiyun u_int8_t slot_info; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define HPEE_SLOT_FEATURES_ENABLE 0x01 47*4882a593Smuzhiyun #define HPEE_SLOT_FEATURES_IOCHK 0x02 48*4882a593Smuzhiyun #define HPEE_SLOT_FEATURES_CFG_INCOMPLETE 0x80 49*4882a593Smuzhiyun u_int8_t slot_features; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u_int8_t ver_min; 52*4882a593Smuzhiyun u_int8_t ver_maj; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_TYPE 0x01 55*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_MEMORY 0x02 56*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_IRQ 0x04 57*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_DMA 0x08 58*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_PORT 0x10 59*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_PORT_INIT 0x20 60*4882a593Smuzhiyun /* I think there are two slighty different 61*4882a593Smuzhiyun * versions of the function_info field 62*4882a593Smuzhiyun * one int the fixed header and one optional 63*4882a593Smuzhiyun * in the parsed slot data area */ 64*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_HAVE_FUNCTION 0x01 65*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_F_DISABLED 0x80 66*4882a593Smuzhiyun #define HPEE_FUNCTION_INFO_CFG_FREE_FORM 0x40 67*4882a593Smuzhiyun u_int8_t function_info; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define HPEE_FLAG_BOARD_IS_ISA 0x01 /* flag and minor version for isa board */ 70*4882a593Smuzhiyun u_int8_t flags; 71*4882a593Smuzhiyun u_int8_t pad[24]; 72*4882a593Smuzhiyun } __attribute__ ((packed)); 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define HPEE_MEMORY_MAX_ENT 9 76*4882a593Smuzhiyun /* memory descriptor: byte 0 */ 77*4882a593Smuzhiyun #define HPEE_MEMORY_WRITABLE 0x01 78*4882a593Smuzhiyun #define HPEE_MEMORY_CACHABLE 0x02 79*4882a593Smuzhiyun #define HPEE_MEMORY_TYPE_MASK 0x18 80*4882a593Smuzhiyun #define HPEE_MEMORY_TYPE_SYS 0x00 81*4882a593Smuzhiyun #define HPEE_MEMORY_TYPE_EXP 0x08 82*4882a593Smuzhiyun #define HPEE_MEMORY_TYPE_VIR 0x10 83*4882a593Smuzhiyun #define HPEE_MEMORY_TYPE_OTH 0x18 84*4882a593Smuzhiyun #define HPEE_MEMORY_SHARED 0x20 85*4882a593Smuzhiyun #define HPEE_MEMORY_MORE 0x80 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* memory descriptor: byte 1 */ 88*4882a593Smuzhiyun #define HPEE_MEMORY_WIDTH_MASK 0x03 89*4882a593Smuzhiyun #define HPEE_MEMORY_WIDTH_BYTE 0x00 90*4882a593Smuzhiyun #define HPEE_MEMORY_WIDTH_WORD 0x01 91*4882a593Smuzhiyun #define HPEE_MEMORY_WIDTH_DWORD 0x02 92*4882a593Smuzhiyun #define HPEE_MEMORY_DECODE_MASK 0x0c 93*4882a593Smuzhiyun #define HPEE_MEMORY_DECODE_20BITS 0x00 94*4882a593Smuzhiyun #define HPEE_MEMORY_DECODE_24BITS 0x04 95*4882a593Smuzhiyun #define HPEE_MEMORY_DECODE_32BITS 0x08 96*4882a593Smuzhiyun /* byte 2 and 3 are a 16bit LE value 97*4882a593Smuzhiyun * containing the memory size in kilobytes */ 98*4882a593Smuzhiyun /* byte 4,5,6 are a 24bit LE value 99*4882a593Smuzhiyun * containing the memory base address */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define HPEE_IRQ_MAX_ENT 7 103*4882a593Smuzhiyun /* Interrupt entry: byte 0 */ 104*4882a593Smuzhiyun #define HPEE_IRQ_CHANNEL_MASK 0xf 105*4882a593Smuzhiyun #define HPEE_IRQ_TRIG_LEVEL 0x20 106*4882a593Smuzhiyun #define HPEE_IRQ_MORE 0x80 107*4882a593Smuzhiyun /* byte 1 seems to be unused */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define HPEE_DMA_MAX_ENT 4 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* dma entry: byte 0 */ 112*4882a593Smuzhiyun #define HPEE_DMA_CHANNEL_MASK 7 113*4882a593Smuzhiyun #define HPEE_DMA_SIZE_MASK 0xc 114*4882a593Smuzhiyun #define HPEE_DMA_SIZE_BYTE 0x0 115*4882a593Smuzhiyun #define HPEE_DMA_SIZE_WORD 0x4 116*4882a593Smuzhiyun #define HPEE_DMA_SIZE_DWORD 0x8 117*4882a593Smuzhiyun #define HPEE_DMA_SHARED 0x40 118*4882a593Smuzhiyun #define HPEE_DMA_MORE 0x80 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* dma entry: byte 1 */ 121*4882a593Smuzhiyun #define HPEE_DMA_TIMING_MASK 0x30 122*4882a593Smuzhiyun #define HPEE_DMA_TIMING_ISA 0x0 123*4882a593Smuzhiyun #define HPEE_DMA_TIMING_TYPEA 0x10 124*4882a593Smuzhiyun #define HPEE_DMA_TIMING_TYPEB 0x20 125*4882a593Smuzhiyun #define HPEE_DMA_TIMING_TYPEC 0x30 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define HPEE_PORT_MAX_ENT 20 128*4882a593Smuzhiyun /* port entry byte 0 */ 129*4882a593Smuzhiyun #define HPEE_PORT_SIZE_MASK 0x1f 130*4882a593Smuzhiyun #define HPEE_PORT_SHARED 0x40 131*4882a593Smuzhiyun #define HPEE_PORT_MORE 0x80 132*4882a593Smuzhiyun /* byte 1 and 2 is a 16bit LE value 133*4882a593Smuzhiyun * containing the start port number */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define HPEE_PORT_INIT_MAX_LEN 60 /* in bytes here */ 136*4882a593Smuzhiyun /* port init entry byte 0 */ 137*4882a593Smuzhiyun #define HPEE_PORT_INIT_WIDTH_MASK 0x3 138*4882a593Smuzhiyun #define HPEE_PORT_INIT_WIDTH_BYTE 0x0 139*4882a593Smuzhiyun #define HPEE_PORT_INIT_WIDTH_WORD 0x1 140*4882a593Smuzhiyun #define HPEE_PORT_INIT_WIDTH_DWORD 0x2 141*4882a593Smuzhiyun #define HPEE_PORT_INIT_MASK 0x4 142*4882a593Smuzhiyun #define HPEE_PORT_INIT_MORE 0x80 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define HPEE_SELECTION_MAX_ENT 26 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define HPEE_TYPE_MAX_LEN 80 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #endif 149