1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/asm-parisc/cache.h 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __ARCH_PARISC_CACHE_H 7*4882a593Smuzhiyun #define __ARCH_PARISC_CACHE_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/alternative.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors 13*4882a593Smuzhiyun * have 32-byte cachelines. The L1 length appears to be 16 bytes but this 14*4882a593Smuzhiyun * is not clearly documented. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define L1_CACHE_BYTES 16 17*4882a593Smuzhiyun #define L1_CACHE_SHIFT 4 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SMP_CACHE_BYTES L1_CACHE_BYTES 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define __read_mostly __section(".data..read_mostly") 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun void parisc_cache_init(void); /* initializes cache-flushing */ 28*4882a593Smuzhiyun void disable_sr_hashing_asm(int); /* low level support for above */ 29*4882a593Smuzhiyun void disable_sr_hashing(void); /* turns off space register hashing */ 30*4882a593Smuzhiyun void free_sid(unsigned long); 31*4882a593Smuzhiyun unsigned long alloc_sid(void); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct seq_file; 34*4882a593Smuzhiyun extern void show_cache_info(struct seq_file *m); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun extern int split_tlb; 37*4882a593Smuzhiyun extern int dcache_stride; 38*4882a593Smuzhiyun extern int icache_stride; 39*4882a593Smuzhiyun extern struct pdc_cache_info cache_info; 40*4882a593Smuzhiyun void parisc_setup_cache_timing(void); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \ 43*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ 44*4882a593Smuzhiyun : : "r" (addr) : "memory") 45*4882a593Smuzhiyun #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \ 46*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ 47*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \ 48*4882a593Smuzhiyun : : "r" (addr) : "memory") 49*4882a593Smuzhiyun #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \ 50*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ 51*4882a593Smuzhiyun : : "r" (addr) : "memory") 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \ 54*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ 55*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \ 56*4882a593Smuzhiyun : : "r" (addr) : "memory") 57*4882a593Smuzhiyun #define asm_io_sync() asm volatile("sync" \ 58*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ 59*4882a593Smuzhiyun ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory") 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* ! __ASSEMBLY__ */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Classes of processor wrt: disabling space register hashing */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ 66*4882a593Smuzhiyun #define SRHASH_PCXL 1 /* pcxl */ 67*4882a593Smuzhiyun #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70