1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OpenRISC Linux 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Linux architectural port borrowing liberally from similar works of 6*4882a593Smuzhiyun * others. All original copyrights apply as per the original source 7*4882a593Smuzhiyun * declaration. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * OpenRISC implementation: 10*4882a593Smuzhiyun * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de> 11*4882a593Smuzhiyun * et al. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ASM_CACHEFLUSH_H 15*4882a593Smuzhiyun #define __ASM_CACHEFLUSH_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/mm.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * Helper function for flushing or invalidating entire pages from data 21*4882a593Smuzhiyun * and instruction caches. SMP needs a little extra work, since we need 22*4882a593Smuzhiyun * to flush the pages on all cpus. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun extern void local_dcache_page_flush(struct page *page); 25*4882a593Smuzhiyun extern void local_icache_page_inv(struct page *page); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Data cache flushing always happen on the local cpu. Instruction cache 29*4882a593Smuzhiyun * invalidations need to be broadcasted to all other cpu in the system in 30*4882a593Smuzhiyun * case of SMP configurations. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #ifndef CONFIG_SMP 33*4882a593Smuzhiyun #define dcache_page_flush(page) local_dcache_page_flush(page) 34*4882a593Smuzhiyun #define icache_page_inv(page) local_icache_page_inv(page) 35*4882a593Smuzhiyun #else /* CONFIG_SMP */ 36*4882a593Smuzhiyun #define dcache_page_flush(page) local_dcache_page_flush(page) 37*4882a593Smuzhiyun #define icache_page_inv(page) smp_icache_page_inv(page) 38*4882a593Smuzhiyun extern void smp_icache_page_inv(struct page *page); 39*4882a593Smuzhiyun #endif /* CONFIG_SMP */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Synchronizes caches. Whenever a cpu writes executable code to memory, this 43*4882a593Smuzhiyun * should be called to make sure the processor sees the newly written code. 44*4882a593Smuzhiyun */ sync_icache_dcache(struct page * page)45*4882a593Smuzhiyunstatic inline void sync_icache_dcache(struct page *page) 46*4882a593Smuzhiyun { 47*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH)) 48*4882a593Smuzhiyun dcache_page_flush(page); 49*4882a593Smuzhiyun icache_page_inv(page); 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * Pages with this bit set need not be flushed/invalidated, since 54*4882a593Smuzhiyun * they have not changed since last flush. New pages start with 55*4882a593Smuzhiyun * PG_arch_1 not set and are therefore dirty by default. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define PG_dc_clean PG_arch_1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 flush_dcache_page(struct page * page)60*4882a593Smuzhiyunstatic inline void flush_dcache_page(struct page *page) 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun clear_bit(PG_dc_clean, &page->flags); 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define flush_icache_user_page(vma, page, addr, len) \ 66*4882a593Smuzhiyun do { \ 67*4882a593Smuzhiyun if (vma->vm_flags & VM_EXEC) \ 68*4882a593Smuzhiyun sync_icache_dcache(page); \ 69*4882a593Smuzhiyun } while (0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #include <asm-generic/cacheflush.h> 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __ASM_CACHEFLUSH_H */ 74