1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2013 Altera Corporation
4*4882a593Smuzhiyun * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
5*4882a593Smuzhiyun * Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * based on irq.c from m68k which is:
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 2007 Greg Ungerer <gerg@snapgear.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static u32 ienable;
17*4882a593Smuzhiyun
do_IRQ(int hwirq,struct pt_regs * regs)18*4882a593Smuzhiyun asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct pt_regs *oldregs = set_irq_regs(regs);
21*4882a593Smuzhiyun int irq;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun irq_enter();
24*4882a593Smuzhiyun irq = irq_find_mapping(NULL, hwirq);
25*4882a593Smuzhiyun generic_handle_irq(irq);
26*4882a593Smuzhiyun irq_exit();
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun set_irq_regs(oldregs);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
chip_unmask(struct irq_data * d)31*4882a593Smuzhiyun static void chip_unmask(struct irq_data *d)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun ienable |= (1 << d->hwirq);
34*4882a593Smuzhiyun WRCTL(CTL_IENABLE, ienable);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
chip_mask(struct irq_data * d)37*4882a593Smuzhiyun static void chip_mask(struct irq_data *d)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun ienable &= ~(1 << d->hwirq);
40*4882a593Smuzhiyun WRCTL(CTL_IENABLE, ienable);
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static struct irq_chip m_irq_chip = {
44*4882a593Smuzhiyun .name = "NIOS2-INTC",
45*4882a593Smuzhiyun .irq_unmask = chip_unmask,
46*4882a593Smuzhiyun .irq_mask = chip_mask,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw_irq_num)49*4882a593Smuzhiyun static int irq_map(struct irq_domain *h, unsigned int virq,
50*4882a593Smuzhiyun irq_hw_number_t hw_irq_num)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun irq_set_chip_and_handler(virq, &m_irq_chip, handle_level_irq);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static const struct irq_domain_ops irq_ops = {
58*4882a593Smuzhiyun .map = irq_map,
59*4882a593Smuzhiyun .xlate = irq_domain_xlate_onecell,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
init_IRQ(void)62*4882a593Smuzhiyun void __init init_IRQ(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct irq_domain *domain;
65*4882a593Smuzhiyun struct device_node *node;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun node = of_find_compatible_node(NULL, NULL, "altr,nios2-1.0");
68*4882a593Smuzhiyun if (!node)
69*4882a593Smuzhiyun node = of_find_compatible_node(NULL, NULL, "altr,nios2-1.1");
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun BUG_ON(!node);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun domain = irq_domain_add_linear(node, NIOS2_CPU_NR_IRQS, &irq_ops, NULL);
74*4882a593Smuzhiyun BUG_ON(!domain);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun irq_set_default_host(domain);
77*4882a593Smuzhiyun of_node_put(node);
78*4882a593Smuzhiyun /* Load the initial ienable value */
79*4882a593Smuzhiyun ienable = RDCTL(CTL_IENABLE);
80*4882a593Smuzhiyun }
81