1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_NIOS2_REGISTERS_H 7*4882a593Smuzhiyun #define _ASM_NIOS2_REGISTERS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 10*4882a593Smuzhiyun #include <asm/cpuinfo.h> 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* control register numbers */ 14*4882a593Smuzhiyun #define CTL_FSTATUS 0 15*4882a593Smuzhiyun #define CTL_ESTATUS 1 16*4882a593Smuzhiyun #define CTL_BSTATUS 2 17*4882a593Smuzhiyun #define CTL_IENABLE 3 18*4882a593Smuzhiyun #define CTL_IPENDING 4 19*4882a593Smuzhiyun #define CTL_CPUID 5 20*4882a593Smuzhiyun #define CTL_RSV1 6 21*4882a593Smuzhiyun #define CTL_EXCEPTION 7 22*4882a593Smuzhiyun #define CTL_PTEADDR 8 23*4882a593Smuzhiyun #define CTL_TLBACC 9 24*4882a593Smuzhiyun #define CTL_TLBMISC 10 25*4882a593Smuzhiyun #define CTL_RSV2 11 26*4882a593Smuzhiyun #define CTL_BADADDR 12 27*4882a593Smuzhiyun #define CTL_CONFIG 13 28*4882a593Smuzhiyun #define CTL_MPUBASE 14 29*4882a593Smuzhiyun #define CTL_MPUACC 15 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* access control registers using GCC builtins */ 32*4882a593Smuzhiyun #define RDCTL(r) __builtin_rdctl(r) 33*4882a593Smuzhiyun #define WRCTL(r, v) __builtin_wrctl(r, v) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* status register bits */ 36*4882a593Smuzhiyun #define STATUS_PIE (1 << 0) /* processor interrupt enable */ 37*4882a593Smuzhiyun #define STATUS_U (1 << 1) /* user mode */ 38*4882a593Smuzhiyun #define STATUS_EH (1 << 2) /* Exception mode */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* estatus register bits */ 41*4882a593Smuzhiyun #define ESTATUS_EPIE (1 << 0) /* processor interrupt enable */ 42*4882a593Smuzhiyun #define ESTATUS_EU (1 << 1) /* user mode */ 43*4882a593Smuzhiyun #define ESTATUS_EH (1 << 2) /* Exception mode */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* tlbmisc register bits */ 46*4882a593Smuzhiyun #define TLBMISC_PID_SHIFT 4 47*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 48*4882a593Smuzhiyun #define TLBMISC_PID_MASK ((1UL << cpuinfo.tlb_pid_num_bits) - 1) 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun #define TLBMISC_WAY_MASK 0xf 51*4882a593Smuzhiyun #define TLBMISC_WAY_SHIFT 20 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TLBMISC_PID (TLBMISC_PID_MASK << TLBMISC_PID_SHIFT) /* TLB PID */ 54*4882a593Smuzhiyun #define TLBMISC_WE (1 << 18) /* TLB write enable */ 55*4882a593Smuzhiyun #define TLBMISC_RD (1 << 19) /* TLB read */ 56*4882a593Smuzhiyun #define TLBMISC_WAY (TLBMISC_WAY_MASK << TLBMISC_WAY_SHIFT) /* TLB way */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _ASM_NIOS2_REGISTERS_H */ 59