1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _ASM_NIOS2_CPUINFO_H 7*4882a593Smuzhiyun #define _ASM_NIOS2_CPUINFO_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct cpuinfo { 12*4882a593Smuzhiyun /* Core CPU configuration */ 13*4882a593Smuzhiyun char cpu_impl[12]; 14*4882a593Smuzhiyun u32 cpu_clock_freq; 15*4882a593Smuzhiyun bool mmu; 16*4882a593Smuzhiyun bool has_div; 17*4882a593Smuzhiyun bool has_mul; 18*4882a593Smuzhiyun bool has_mulx; 19*4882a593Smuzhiyun bool has_bmx; 20*4882a593Smuzhiyun bool has_cdx; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* CPU caches */ 23*4882a593Smuzhiyun u32 icache_line_size; 24*4882a593Smuzhiyun u32 icache_size; 25*4882a593Smuzhiyun u32 dcache_line_size; 26*4882a593Smuzhiyun u32 dcache_size; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TLB */ 29*4882a593Smuzhiyun u32 tlb_pid_num_bits; /* number of bits used for the PID in TLBMISC */ 30*4882a593Smuzhiyun u32 tlb_num_ways; 31*4882a593Smuzhiyun u32 tlb_num_ways_log2; 32*4882a593Smuzhiyun u32 tlb_num_entries; 33*4882a593Smuzhiyun u32 tlb_num_lines; 34*4882a593Smuzhiyun u32 tlb_ptr_sz; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Addresses */ 37*4882a593Smuzhiyun u32 reset_addr; 38*4882a593Smuzhiyun u32 exception_addr; 39*4882a593Smuzhiyun u32 fast_tlb_miss_exc_addr; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun extern struct cpuinfo cpuinfo; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun extern void setup_cpuinfo(void); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* _ASM_NIOS2_CPUINFO_H */ 47