1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2004 Microtronix Datacom Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_NIOS2_CACHE_H 9*4882a593Smuzhiyun #define _ASM_NIOS2_CACHE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define NIOS2_DCACHE_SIZE CONFIG_NIOS2_DCACHE_SIZE 12*4882a593Smuzhiyun #define NIOS2_ICACHE_SIZE CONFIG_NIOS2_ICACHE_SIZE 13*4882a593Smuzhiyun #define NIOS2_DCACHE_LINE_SIZE CONFIG_NIOS2_DCACHE_LINE_SIZE 14*4882a593Smuzhiyun #define NIOS2_ICACHE_LINE_SHIFT 5 15*4882a593Smuzhiyun #define NIOS2_ICACHE_LINE_SIZE (1 << NIOS2_ICACHE_LINE_SHIFT) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* bytes per L1 cache line */ 18*4882a593Smuzhiyun #define L1_CACHE_SHIFT NIOS2_ICACHE_LINE_SHIFT 19*4882a593Smuzhiyun #define L1_CACHE_BYTES NIOS2_ICACHE_LINE_SIZE 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define __cacheline_aligned 24*4882a593Smuzhiyun #define ____cacheline_aligned 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif 27