1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2010 Thomas Chou <thomas@wytron.com.tw> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include <linux/io.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #if (defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE) && defined(JTAG_UART_BASE))\ 9*4882a593Smuzhiyun || (defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE) && defined(UART0_BASE)) my_ioremap(unsigned long physaddr)10*4882a593Smuzhiyunstatic void *my_ioremap(unsigned long physaddr) 11*4882a593Smuzhiyun { 12*4882a593Smuzhiyun return (void *)(physaddr | CONFIG_NIOS2_IO_REGION_BASE); 13*4882a593Smuzhiyun } 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE) && defined(JTAG_UART_BASE) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define ALTERA_JTAGUART_SIZE 8 19*4882a593Smuzhiyun #define ALTERA_JTAGUART_DATA_REG 0 20*4882a593Smuzhiyun #define ALTERA_JTAGUART_CONTROL_REG 4 21*4882a593Smuzhiyun #define ALTERA_JTAGUART_CONTROL_AC_MSK (0x00000400) 22*4882a593Smuzhiyun #define ALTERA_JTAGUART_CONTROL_WSPACE_MSK (0xFFFF0000) 23*4882a593Smuzhiyun static void *uartbase; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #if defined(CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS) jtag_putc(int ch)26*4882a593Smuzhiyunstatic void jtag_putc(int ch) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun if (readl(uartbase + ALTERA_JTAGUART_CONTROL_REG) & 29*4882a593Smuzhiyun ALTERA_JTAGUART_CONTROL_WSPACE_MSK) 30*4882a593Smuzhiyun writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG); 31*4882a593Smuzhiyun } 32*4882a593Smuzhiyun #else jtag_putc(int ch)33*4882a593Smuzhiyunstatic void jtag_putc(int ch) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun while ((readl(uartbase + ALTERA_JTAGUART_CONTROL_REG) & 36*4882a593Smuzhiyun ALTERA_JTAGUART_CONTROL_WSPACE_MSK) == 0) 37*4882a593Smuzhiyun ; 38*4882a593Smuzhiyun writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun putchar(int ch)42*4882a593Smuzhiyunstatic int putchar(int ch) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun jtag_putc(ch); 45*4882a593Smuzhiyun return ch; 46*4882a593Smuzhiyun } 47*4882a593Smuzhiyun console_init(void)48*4882a593Smuzhiyunstatic void console_init(void) 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun uartbase = my_ioremap((unsigned long) JTAG_UART_BASE); 51*4882a593Smuzhiyun writel(ALTERA_JTAGUART_CONTROL_AC_MSK, 52*4882a593Smuzhiyun uartbase + ALTERA_JTAGUART_CONTROL_REG); 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #elif defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE) && defined(UART0_BASE) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define ALTERA_UART_SIZE 32 58*4882a593Smuzhiyun #define ALTERA_UART_TXDATA_REG 4 59*4882a593Smuzhiyun #define ALTERA_UART_STATUS_REG 8 60*4882a593Smuzhiyun #define ALTERA_UART_DIVISOR_REG 16 61*4882a593Smuzhiyun #define ALTERA_UART_STATUS_TRDY_MSK (0x40) 62*4882a593Smuzhiyun static unsigned uartbase; 63*4882a593Smuzhiyun uart_putc(int ch)64*4882a593Smuzhiyunstatic void uart_putc(int ch) 65*4882a593Smuzhiyun { 66*4882a593Smuzhiyun int i; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun for (i = 0; (i < 0x10000); i++) { 69*4882a593Smuzhiyun if (readw(uartbase + ALTERA_UART_STATUS_REG) & 70*4882a593Smuzhiyun ALTERA_UART_STATUS_TRDY_MSK) 71*4882a593Smuzhiyun break; 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun writeb(ch, uartbase + ALTERA_UART_TXDATA_REG); 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun putchar(int ch)76*4882a593Smuzhiyunstatic int putchar(int ch) 77*4882a593Smuzhiyun { 78*4882a593Smuzhiyun uart_putc(ch); 79*4882a593Smuzhiyun if (ch == '\n') 80*4882a593Smuzhiyun uart_putc('\r'); 81*4882a593Smuzhiyun return ch; 82*4882a593Smuzhiyun } 83*4882a593Smuzhiyun console_init(void)84*4882a593Smuzhiyunstatic void console_init(void) 85*4882a593Smuzhiyun { 86*4882a593Smuzhiyun unsigned int baud, baudclk; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun uartbase = (unsigned long) my_ioremap((unsigned long) UART0_BASE); 89*4882a593Smuzhiyun baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE; 90*4882a593Smuzhiyun baudclk = UART0_FREQ / baud; 91*4882a593Smuzhiyun writew(baudclk, uartbase + ALTERA_UART_DIVISOR_REG); 92*4882a593Smuzhiyun } 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #else 95*4882a593Smuzhiyun putchar(int ch)96*4882a593Smuzhiyunstatic int putchar(int ch) 97*4882a593Smuzhiyun { 98*4882a593Smuzhiyun return ch; 99*4882a593Smuzhiyun } 100*4882a593Smuzhiyun console_init(void)101*4882a593Smuzhiyunstatic void console_init(void) 102*4882a593Smuzhiyun { 103*4882a593Smuzhiyun } 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun puts(const char * s)107*4882a593Smuzhiyunstatic int puts(const char *s) 108*4882a593Smuzhiyun { 109*4882a593Smuzhiyun while (*s) 110*4882a593Smuzhiyun putchar(*s++); 111*4882a593Smuzhiyun return 0; 112*4882a593Smuzhiyun } 113