1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) 2005-2017 Andes Technology Corporation
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/types.h>
5*4882a593Smuzhiyun #include <linux/mm.h>
6*4882a593Smuzhiyun #include <linux/dma-map-ops.h>
7*4882a593Smuzhiyun #include <linux/cache.h>
8*4882a593Smuzhiyun #include <linux/highmem.h>
9*4882a593Smuzhiyun #include <asm/cacheflush.h>
10*4882a593Smuzhiyun #include <asm/tlbflush.h>
11*4882a593Smuzhiyun #include <asm/proc-fns.h>
12*4882a593Smuzhiyun
cache_op(phys_addr_t paddr,size_t size,void (* fn)(unsigned long start,unsigned long end))13*4882a593Smuzhiyun static inline void cache_op(phys_addr_t paddr, size_t size,
14*4882a593Smuzhiyun void (*fn)(unsigned long start, unsigned long end))
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
17*4882a593Smuzhiyun unsigned offset = paddr & ~PAGE_MASK;
18*4882a593Smuzhiyun size_t left = size;
19*4882a593Smuzhiyun unsigned long start;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun do {
22*4882a593Smuzhiyun size_t len = left;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun if (PageHighMem(page)) {
25*4882a593Smuzhiyun void *addr;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun if (offset + len > PAGE_SIZE) {
28*4882a593Smuzhiyun if (offset >= PAGE_SIZE) {
29*4882a593Smuzhiyun page += offset >> PAGE_SHIFT;
30*4882a593Smuzhiyun offset &= ~PAGE_MASK;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun len = PAGE_SIZE - offset;
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun addr = kmap_atomic(page);
36*4882a593Smuzhiyun start = (unsigned long)(addr + offset);
37*4882a593Smuzhiyun fn(start, start + len);
38*4882a593Smuzhiyun kunmap_atomic(addr);
39*4882a593Smuzhiyun } else {
40*4882a593Smuzhiyun start = (unsigned long)phys_to_virt(paddr);
41*4882a593Smuzhiyun fn(start, start + size);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun offset = 0;
44*4882a593Smuzhiyun page++;
45*4882a593Smuzhiyun left -= len;
46*4882a593Smuzhiyun } while (left);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
arch_sync_dma_for_device(phys_addr_t paddr,size_t size,enum dma_data_direction dir)49*4882a593Smuzhiyun void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
50*4882a593Smuzhiyun enum dma_data_direction dir)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun switch (dir) {
53*4882a593Smuzhiyun case DMA_FROM_DEVICE:
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun case DMA_TO_DEVICE:
56*4882a593Smuzhiyun case DMA_BIDIRECTIONAL:
57*4882a593Smuzhiyun cache_op(paddr, size, cpu_dma_wb_range);
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun default:
60*4882a593Smuzhiyun BUG();
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
arch_sync_dma_for_cpu(phys_addr_t paddr,size_t size,enum dma_data_direction dir)64*4882a593Smuzhiyun void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
65*4882a593Smuzhiyun enum dma_data_direction dir)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun switch (dir) {
68*4882a593Smuzhiyun case DMA_TO_DEVICE:
69*4882a593Smuzhiyun break;
70*4882a593Smuzhiyun case DMA_FROM_DEVICE:
71*4882a593Smuzhiyun case DMA_BIDIRECTIONAL:
72*4882a593Smuzhiyun cache_op(paddr, size, cpu_dma_inval_range);
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun default:
75*4882a593Smuzhiyun BUG();
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
arch_dma_prep_coherent(struct page * page,size_t size)79*4882a593Smuzhiyun void arch_dma_prep_coherent(struct page *page, size_t size)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun cache_op(page_to_phys(page), size, cpu_dma_wbinval_range);
82*4882a593Smuzhiyun }
83