1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2005-2018 Andes Technology Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __NDS32_FPU_INST_H 5*4882a593Smuzhiyun #define __NDS32_FPU_INST_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define cop0_op 0x35 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * COP0 field of opcodes. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun #define fs1_op 0x0 13*4882a593Smuzhiyun #define fs2_op 0x4 14*4882a593Smuzhiyun #define fd1_op 0x8 15*4882a593Smuzhiyun #define fd2_op 0xc 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * FS1 opcode. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun enum fs1 { 21*4882a593Smuzhiyun fadds_op, fsubs_op, fcpynss_op, fcpyss_op, 22*4882a593Smuzhiyun fmadds_op, fmsubs_op, fcmovns_op, fcmovzs_op, 23*4882a593Smuzhiyun fnmadds_op, fnmsubs_op, 24*4882a593Smuzhiyun fmuls_op = 0xc, fdivs_op, 25*4882a593Smuzhiyun fs1_f2op_op = 0xf 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * FS1/F2OP opcode. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun enum fs1_f2 { 32*4882a593Smuzhiyun fs2d_op, fsqrts_op, 33*4882a593Smuzhiyun fui2s_op = 0x8, fsi2s_op = 0xc, 34*4882a593Smuzhiyun fs2ui_op = 0x10, fs2ui_z_op = 0x14, 35*4882a593Smuzhiyun fs2si_op = 0x18, fs2si_z_op = 0x1c 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * FS2 opcode. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun enum fs2 { 42*4882a593Smuzhiyun fcmpeqs_op, fcmpeqs_e_op, fcmplts_op, fcmplts_e_op, 43*4882a593Smuzhiyun fcmples_op, fcmples_e_op, fcmpuns_op, fcmpuns_e_op 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * FD1 opcode. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun enum fd1 { 50*4882a593Smuzhiyun faddd_op, fsubd_op, fcpynsd_op, fcpysd_op, 51*4882a593Smuzhiyun fmaddd_op, fmsubd_op, fcmovnd_op, fcmovzd_op, 52*4882a593Smuzhiyun fnmaddd_op, fnmsubd_op, 53*4882a593Smuzhiyun fmuld_op = 0xc, fdivd_op, fd1_f2op_op = 0xf 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * FD1/F2OP opcode. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun enum fd1_f2 { 60*4882a593Smuzhiyun fd2s_op, fsqrtd_op, 61*4882a593Smuzhiyun fui2d_op = 0x8, fsi2d_op = 0xc, 62*4882a593Smuzhiyun fd2ui_op = 0x10, fd2ui_z_op = 0x14, 63*4882a593Smuzhiyun fd2si_op = 0x18, fd2si_z_op = 0x1c 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * FD2 opcode. 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun enum fd2 { 70*4882a593Smuzhiyun fcmpeqd_op, fcmpeqd_e_op, fcmpltd_op, fcmpltd_e_op, 71*4882a593Smuzhiyun fcmpled_op, fcmpled_e_op, fcmpund_op, fcmpund_e_op 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define NDS32Insn(x) x 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define I_OPCODE_off 25 77*4882a593Smuzhiyun #define NDS32Insn_OPCODE(x) (NDS32Insn(x) >> I_OPCODE_off) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define I_OPCODE_offRt 20 80*4882a593Smuzhiyun #define I_OPCODE_mskRt (0x1fUL << I_OPCODE_offRt) 81*4882a593Smuzhiyun #define NDS32Insn_OPCODE_Rt(x) \ 82*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskRt) >> I_OPCODE_offRt) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define I_OPCODE_offRa 15 85*4882a593Smuzhiyun #define I_OPCODE_mskRa (0x1fUL << I_OPCODE_offRa) 86*4882a593Smuzhiyun #define NDS32Insn_OPCODE_Ra(x) \ 87*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskRa) >> I_OPCODE_offRa) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define I_OPCODE_offRb 10 90*4882a593Smuzhiyun #define I_OPCODE_mskRb (0x1fUL << I_OPCODE_offRb) 91*4882a593Smuzhiyun #define NDS32Insn_OPCODE_Rb(x) \ 92*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskRb) >> I_OPCODE_offRb) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define I_OPCODE_offbit1014 10 95*4882a593Smuzhiyun #define I_OPCODE_mskbit1014 (0x1fUL << I_OPCODE_offbit1014) 96*4882a593Smuzhiyun #define NDS32Insn_OPCODE_BIT1014(x) \ 97*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskbit1014) >> I_OPCODE_offbit1014) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define I_OPCODE_offbit69 6 100*4882a593Smuzhiyun #define I_OPCODE_mskbit69 (0xfUL << I_OPCODE_offbit69) 101*4882a593Smuzhiyun #define NDS32Insn_OPCODE_BIT69(x) \ 102*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskbit69) >> I_OPCODE_offbit69) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define I_OPCODE_offCOP0 0 105*4882a593Smuzhiyun #define I_OPCODE_mskCOP0 (0x3fUL << I_OPCODE_offCOP0) 106*4882a593Smuzhiyun #define NDS32Insn_OPCODE_COP0(x) \ 107*4882a593Smuzhiyun ((NDS32Insn(x) & I_OPCODE_mskCOP0) >> I_OPCODE_offCOP0) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif /* __NDS32_FPU_INST_H */ 110