1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun // Copyright (C) 2005-2017 Andes Technology Corporation
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef __ASM_NDS32_IO_H
5*4882a593Smuzhiyun #define __ASM_NDS32_IO_H
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define __raw_writeb __raw_writeb
__raw_writeb(u8 val,volatile void __iomem * addr)10*4882a593Smuzhiyun static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
13*4882a593Smuzhiyun }
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define __raw_writew __raw_writew
__raw_writew(u16 val,volatile void __iomem * addr)16*4882a593Smuzhiyun static inline void __raw_writew(u16 val, volatile void __iomem *addr)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
19*4882a593Smuzhiyun }
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define __raw_writel __raw_writel
__raw_writel(u32 val,volatile void __iomem * addr)22*4882a593Smuzhiyun static inline void __raw_writel(u32 val, volatile void __iomem *addr)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define __raw_readb __raw_readb
__raw_readb(const volatile void __iomem * addr)28*4882a593Smuzhiyun static inline u8 __raw_readb(const volatile void __iomem *addr)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun u8 val;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
33*4882a593Smuzhiyun return val;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define __raw_readw __raw_readw
__raw_readw(const volatile void __iomem * addr)37*4882a593Smuzhiyun static inline u16 __raw_readw(const volatile void __iomem *addr)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun u16 val;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
42*4882a593Smuzhiyun return val;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define __raw_readl __raw_readl
__raw_readl(const volatile void __iomem * addr)46*4882a593Smuzhiyun static inline u32 __raw_readl(const volatile void __iomem *addr)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun u32 val;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
51*4882a593Smuzhiyun return val;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define __iormb() rmb()
55*4882a593Smuzhiyun #define __iowmb() wmb()
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
59*4882a593Smuzhiyun * are not guaranteed to provide ordering against spinlocks or memory
60*4882a593Smuzhiyun * accesses.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
64*4882a593Smuzhiyun #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
65*4882a593Smuzhiyun #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
66*4882a593Smuzhiyun #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
67*4882a593Smuzhiyun #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
68*4882a593Smuzhiyun #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * {read,write}{b,w,l,q}() access little endian memory and return result in
72*4882a593Smuzhiyun * native endianness.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
75*4882a593Smuzhiyun #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
76*4882a593Smuzhiyun #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
79*4882a593Smuzhiyun #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
80*4882a593Smuzhiyun #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #include <asm-generic/io.h>
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #endif /* __ASM_NDS32_IO_H */
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