1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun // Copyright (C) 2005-2017 Andes Technology Corporation 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __NDS32_BITFIELD_H__ 5*4882a593Smuzhiyun #define __NDS32_BITFIELD_H__ 6*4882a593Smuzhiyun /****************************************************************************** 7*4882a593Smuzhiyun * cr0: CPU_VER (CPU Version Register) 8*4882a593Smuzhiyun *****************************************************************************/ 9*4882a593Smuzhiyun #define CPU_VER_offCFGID 0 /* Minor configuration */ 10*4882a593Smuzhiyun #define CPU_VER_offREV 16 /* Revision of the CPU version */ 11*4882a593Smuzhiyun #define CPU_VER_offCPUID 24 /* Major CPU versions */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID ) 14*4882a593Smuzhiyun #define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV ) 15*4882a593Smuzhiyun #define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID ) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /****************************************************************************** 18*4882a593Smuzhiyun * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register) 19*4882a593Smuzhiyun *****************************************************************************/ 20*4882a593Smuzhiyun #define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */ 21*4882a593Smuzhiyun #define ICM_CFG_offIWAY 3 /* I-cache ways */ 22*4882a593Smuzhiyun #define ICM_CFG_offISZ 6 /* I-cache line size */ 23*4882a593Smuzhiyun #define ICM_CFG_offILCK 9 /* I-cache locking support */ 24*4882a593Smuzhiyun #define ICM_CFG_offILMB 10 /* On-chip ILM banks */ 25*4882a593Smuzhiyun #define ICM_CFG_offBSAV 13 /* ILM base register alignment version */ 26*4882a593Smuzhiyun /* bit 15:31 reserved */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET ) 29*4882a593Smuzhiyun #define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY ) 30*4882a593Smuzhiyun #define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ ) 31*4882a593Smuzhiyun #define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK ) 32*4882a593Smuzhiyun #define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB ) 33*4882a593Smuzhiyun #define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV ) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /****************************************************************************** 36*4882a593Smuzhiyun * cr2: DCM_CFG (Data Cache/Memory Configuration Register) 37*4882a593Smuzhiyun *****************************************************************************/ 38*4882a593Smuzhiyun #define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */ 39*4882a593Smuzhiyun #define DCM_CFG_offDWAY 3 /* D-cache ways */ 40*4882a593Smuzhiyun #define DCM_CFG_offDSZ 6 /* D-cache line size */ 41*4882a593Smuzhiyun #define DCM_CFG_offDLCK 9 /* D-cache locking support */ 42*4882a593Smuzhiyun #define DCM_CFG_offDLMB 10 /* On-chip DLM banks */ 43*4882a593Smuzhiyun #define DCM_CFG_offBSAV 13 /* DLM base register alignment version */ 44*4882a593Smuzhiyun /* bit 15:31 reserved */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET ) 47*4882a593Smuzhiyun #define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY ) 48*4882a593Smuzhiyun #define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ ) 49*4882a593Smuzhiyun #define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK ) 50*4882a593Smuzhiyun #define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB ) 51*4882a593Smuzhiyun #define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV ) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /****************************************************************************** 54*4882a593Smuzhiyun * cr3: MMU_CFG (MMU Configuration Register) 55*4882a593Smuzhiyun *****************************************************************************/ 56*4882a593Smuzhiyun #define MMU_CFG_offMMPS 0 /* Memory management protection scheme */ 57*4882a593Smuzhiyun #define MMU_CFG_offMMPV 2 /* Memory management protection version number */ 58*4882a593Smuzhiyun #define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */ 61*4882a593Smuzhiyun #define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */ 62*4882a593Smuzhiyun /* bit 14:14 reserved */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */ 65*4882a593Smuzhiyun #define MMU_CFG_offfEPSZ 16 /* Extra page size supported */ 66*4882a593Smuzhiyun #define MMU_CFG_offTLBLCK 24 /* TLB locking support */ 67*4882a593Smuzhiyun #define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */ 68*4882a593Smuzhiyun #define MMU_CFG_offDE 26 /* Default endian */ 69*4882a593Smuzhiyun #define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */ 70*4882a593Smuzhiyun #define MMU_CFG_offIVTB 28 /* Invisible TLB */ 71*4882a593Smuzhiyun #define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */ 72*4882a593Smuzhiyun #define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */ 73*4882a593Smuzhiyun /* bit 31 reserved */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS ) 76*4882a593Smuzhiyun #define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV ) 77*4882a593Smuzhiyun #define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB ) 78*4882a593Smuzhiyun #define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW ) 79*4882a593Smuzhiyun #define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS ) 80*4882a593Smuzhiyun #define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 ) 81*4882a593Smuzhiyun #define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ ) 82*4882a593Smuzhiyun #define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK ) 83*4882a593Smuzhiyun #define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK ) 84*4882a593Smuzhiyun #define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE ) 85*4882a593Smuzhiyun #define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT ) 86*4882a593Smuzhiyun #define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB ) 87*4882a593Smuzhiyun #define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT ) 88*4882a593Smuzhiyun #define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME ) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /****************************************************************************** 91*4882a593Smuzhiyun * cr4: MSC_CFG (Misc Configuration Register) 92*4882a593Smuzhiyun *****************************************************************************/ 93*4882a593Smuzhiyun #define MSC_CFG_offEDM 0 94*4882a593Smuzhiyun #define MSC_CFG_offLMDMA 1 95*4882a593Smuzhiyun #define MSC_CFG_offPFM 2 96*4882a593Smuzhiyun #define MSC_CFG_offHSMP 3 97*4882a593Smuzhiyun #define MSC_CFG_offTRACE 4 98*4882a593Smuzhiyun #define MSC_CFG_offDIV 5 99*4882a593Smuzhiyun #define MSC_CFG_offMAC 6 100*4882a593Smuzhiyun #define MSC_CFG_offAUDIO 7 101*4882a593Smuzhiyun #define MSC_CFG_offL2C 9 102*4882a593Smuzhiyun #define MSC_CFG_offRDREG 10 103*4882a593Smuzhiyun #define MSC_CFG_offADR24 11 104*4882a593Smuzhiyun #define MSC_CFG_offINTLC 12 105*4882a593Smuzhiyun #define MSC_CFG_offBASEV 13 106*4882a593Smuzhiyun #define MSC_CFG_offNOD 16 107*4882a593Smuzhiyun /* bit 13:31 reserved */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM ) 110*4882a593Smuzhiyun #define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA ) 111*4882a593Smuzhiyun #define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM ) 112*4882a593Smuzhiyun #define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP ) 113*4882a593Smuzhiyun #define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE ) 114*4882a593Smuzhiyun #define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV ) 115*4882a593Smuzhiyun #define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC ) 116*4882a593Smuzhiyun #define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO ) 117*4882a593Smuzhiyun #define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C ) 118*4882a593Smuzhiyun #define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG ) 119*4882a593Smuzhiyun #define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 ) 120*4882a593Smuzhiyun #define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC ) 121*4882a593Smuzhiyun #define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV ) 122*4882a593Smuzhiyun #define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD ) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /****************************************************************************** 125*4882a593Smuzhiyun * cr5: CORE_CFG (Core Identification Register) 126*4882a593Smuzhiyun *****************************************************************************/ 127*4882a593Smuzhiyun #define CORE_ID_offCOREID 0 128*4882a593Smuzhiyun /* bit 4:31 reserved */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID ) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /****************************************************************************** 133*4882a593Smuzhiyun * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register) 134*4882a593Smuzhiyun *****************************************************************************/ 135*4882a593Smuzhiyun #define FUCOP_EXIST_offCP0EX 0 136*4882a593Smuzhiyun #define FUCOP_EXIST_offCP1EX 1 137*4882a593Smuzhiyun #define FUCOP_EXIST_offCP2EX 2 138*4882a593Smuzhiyun #define FUCOP_EXIST_offCP3EX 3 139*4882a593Smuzhiyun #define FUCOP_EXIST_offCP0ISFPU 31 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX ) 142*4882a593Smuzhiyun #define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX ) 143*4882a593Smuzhiyun #define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX ) 144*4882a593Smuzhiyun #define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX ) 145*4882a593Smuzhiyun #define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU ) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /****************************************************************************** 148*4882a593Smuzhiyun * ir0: PSW (Processor Status Word Register) 149*4882a593Smuzhiyun * ir1: IPSW (Interruption PSW Register) 150*4882a593Smuzhiyun * ir2: P_IPSW (Previous IPSW Register) 151*4882a593Smuzhiyun *****************************************************************************/ 152*4882a593Smuzhiyun #define PSW_offGIE 0 /* Global Interrupt Enable */ 153*4882a593Smuzhiyun #define PSW_offINTL 1 /* Interruption Stack Level */ 154*4882a593Smuzhiyun #define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */ 155*4882a593Smuzhiyun #define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */ 156*4882a593Smuzhiyun #define PSW_offIT 6 /* Enable instruction address translation */ 157*4882a593Smuzhiyun #define PSW_offDT 7 /* Enable data address translation */ 158*4882a593Smuzhiyun #define PSW_offIME 8 /* Instruction Machine Error flag */ 159*4882a593Smuzhiyun #define PSW_offDME 9 /* Data Machine Error flag */ 160*4882a593Smuzhiyun #define PSW_offDEX 10 /* Debug Exception */ 161*4882a593Smuzhiyun #define PSW_offHSS 11 /* Hardware Single Stepping */ 162*4882a593Smuzhiyun #define PSW_offDRBE 12 /* Device Register Endian Mode */ 163*4882a593Smuzhiyun #define PSW_offAEN 13 /* Audio ISA special feature */ 164*4882a593Smuzhiyun #define PSW_offWBNA 14 /* Write Back Non-Allocate */ 165*4882a593Smuzhiyun #define PSW_offIFCON 15 /* IFC On */ 166*4882a593Smuzhiyun #define PSW_offCPL 16 /* Current Priority Level */ 167*4882a593Smuzhiyun /* bit 19:31 reserved */ 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define PSW_mskGIE ( 0x1 << PSW_offGIE ) 170*4882a593Smuzhiyun #define PSW_mskINTL ( 0x3 << PSW_offINTL ) 171*4882a593Smuzhiyun #define PSW_mskPOM ( 0x3 << PSW_offPOM ) 172*4882a593Smuzhiyun #define PSW_mskBE ( 0x1 << PSW_offBE ) 173*4882a593Smuzhiyun #define PSW_mskIT ( 0x1 << PSW_offIT ) 174*4882a593Smuzhiyun #define PSW_mskDT ( 0x1 << PSW_offDT ) 175*4882a593Smuzhiyun #define PSW_mskIME ( 0x1 << PSW_offIME ) 176*4882a593Smuzhiyun #define PSW_mskDME ( 0x1 << PSW_offDME ) 177*4882a593Smuzhiyun #define PSW_mskDEX ( 0x1 << PSW_offDEX ) 178*4882a593Smuzhiyun #define PSW_mskHSS ( 0x1 << PSW_offHSS ) 179*4882a593Smuzhiyun #define PSW_mskDRBE ( 0x1 << PSW_offDRBE ) 180*4882a593Smuzhiyun #define PSW_mskAEN ( 0x1 << PSW_offAEN ) 181*4882a593Smuzhiyun #define PSW_mskWBNA ( 0x1 << PSW_offWBNA ) 182*4882a593Smuzhiyun #define PSW_mskIFCON ( 0x1 << PSW_offIFCON ) 183*4882a593Smuzhiyun #define PSW_mskCPL ( 0x7 << PSW_offCPL ) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define PSW_SYSTEM ( 1 << PSW_offPOM ) 186*4882a593Smuzhiyun #define PSW_INTL_1 ( 1 << PSW_offINTL ) 187*4882a593Smuzhiyun #define PSW_CPL_NO ( 0 << PSW_offCPL ) 188*4882a593Smuzhiyun #define PSW_CPL_ANY ( 7 << PSW_offCPL ) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA) 191*4882a593Smuzhiyun #ifdef __NDS32_EB__ 192*4882a593Smuzhiyun #ifdef CONFIG_WBNA 193*4882a593Smuzhiyun #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE) 194*4882a593Smuzhiyun #else 195*4882a593Smuzhiyun #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE) 196*4882a593Smuzhiyun #endif 197*4882a593Smuzhiyun #else 198*4882a593Smuzhiyun #ifdef CONFIG_WBNA 199*4882a593Smuzhiyun #define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT) 200*4882a593Smuzhiyun #else 201*4882a593Smuzhiyun #define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT) 202*4882a593Smuzhiyun #endif 203*4882a593Smuzhiyun #endif 204*4882a593Smuzhiyun /****************************************************************************** 205*4882a593Smuzhiyun * ir3: IVB (Interruption Vector Base Register) 206*4882a593Smuzhiyun *****************************************************************************/ 207*4882a593Smuzhiyun /* bit 0:12 reserved */ 208*4882a593Smuzhiyun #define IVB_offNIVIC 1 /* Number of input for IVIC Controller */ 209*4882a593Smuzhiyun #define IVB_offIVIC_VER 11 /* IVIC Version */ 210*4882a593Smuzhiyun #define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */ 211*4882a593Smuzhiyun #define IVB_offESZ 14 /* Size of each vector entry */ 212*4882a593Smuzhiyun #define IVB_offIVBASE 16 /* BasePA of interrupt vector table */ 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC ) 215*4882a593Smuzhiyun #define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER ) 216*4882a593Smuzhiyun #define IVB_mskEVIC ( 0x1 << IVB_offEVIC ) 217*4882a593Smuzhiyun #define IVB_mskESZ ( 0x3 << IVB_offESZ ) 218*4882a593Smuzhiyun #define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE ) 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define IVB_valESZ4 0 221*4882a593Smuzhiyun #define IVB_valESZ16 1 222*4882a593Smuzhiyun #define IVB_valESZ64 2 223*4882a593Smuzhiyun #define IVB_valESZ256 3 224*4882a593Smuzhiyun /****************************************************************************** 225*4882a593Smuzhiyun * ir4: EVA (Exception Virtual Address Register) 226*4882a593Smuzhiyun * ir5: P_EVA (Previous EVA Register) 227*4882a593Smuzhiyun *****************************************************************************/ 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* This register contains the VA that causes the exception */ 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /****************************************************************************** 232*4882a593Smuzhiyun * ir6: ITYPE (Interruption Type Register) 233*4882a593Smuzhiyun * ir7: P_ITYPE (Previous ITYPE Register) 234*4882a593Smuzhiyun *****************************************************************************/ 235*4882a593Smuzhiyun #define ITYPE_offETYPE 0 /* Exception Type */ 236*4882a593Smuzhiyun #define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */ 237*4882a593Smuzhiyun /* bit 5:15 reserved */ 238*4882a593Smuzhiyun #define ITYPE_offVECTOR 5 /* Vector */ 239*4882a593Smuzhiyun #define ITYPE_offSWID 16 /* SWID of debugging exception */ 240*4882a593Smuzhiyun /* bit 31:31 reserved */ 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE ) 243*4882a593Smuzhiyun #define ITYPE_mskINST ( 0x1 << ITYPE_offINST ) 244*4882a593Smuzhiyun #define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR ) 245*4882a593Smuzhiyun #define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID ) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* Additional definitions for ITYPE register */ 248*4882a593Smuzhiyun #define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */ 249*4882a593Smuzhiyun #define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */ 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE ) 252*4882a593Smuzhiyun #define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID ) 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* Additional definitions of ITYPE register for FPU */ 255*4882a593Smuzhiyun #define FPU_DISABLE_EXCEPTION (0x1 << ITYPE_offSTYPE) 256*4882a593Smuzhiyun #define FPU_EXCEPTION (0x2 << ITYPE_offSTYPE) 257*4882a593Smuzhiyun #define FPU_CPID 0 /* FPU Co-Processor ID is 0 */ 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define NDS32_VECTOR_mskNONEXCEPTION 0x78 260*4882a593Smuzhiyun #define NDS32_VECTOR_offEXCEPTION 8 261*4882a593Smuzhiyun #define NDS32_VECTOR_offINTERRUPT 9 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* Interrupt vector entry */ 264*4882a593Smuzhiyun #define ENTRY_RESET_NMI 0 265*4882a593Smuzhiyun #define ENTRY_TLB_FILL 1 266*4882a593Smuzhiyun #define ENTRY_PTE_NOT_PRESENT 2 267*4882a593Smuzhiyun #define ENTRY_TLB_MISC 3 268*4882a593Smuzhiyun #define ENTRY_TLB_VLPT_MISS 4 269*4882a593Smuzhiyun #define ENTRY_MACHINE_ERROR 5 270*4882a593Smuzhiyun #define ENTRY_DEBUG_RELATED 6 271*4882a593Smuzhiyun #define ENTRY_GENERAL_EXCPETION 7 272*4882a593Smuzhiyun #define ENTRY_SYSCALL 8 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* PTE not present exception definition */ 275*4882a593Smuzhiyun #define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0 276*4882a593Smuzhiyun #define ETYPE_LEAF_PTE_NOT_PRESENT 1 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* General exception ETYPE definition */ 279*4882a593Smuzhiyun #define ETYPE_ALIGNMENT_CHECK 0 280*4882a593Smuzhiyun #define ETYPE_RESERVED_INSTRUCTION 1 281*4882a593Smuzhiyun #define ETYPE_TRAP 2 282*4882a593Smuzhiyun #define ETYPE_ARITHMETIC 3 283*4882a593Smuzhiyun #define ETYPE_PRECISE_BUS_ERROR 4 284*4882a593Smuzhiyun #define ETYPE_IMPRECISE_BUS_ERROR 5 285*4882a593Smuzhiyun #define ETYPE_COPROCESSOR 6 286*4882a593Smuzhiyun #define ETYPE_RESERVED_VALUE 7 287*4882a593Smuzhiyun #define ETYPE_NONEXISTENT_MEM_ADDRESS 8 288*4882a593Smuzhiyun #define ETYPE_MPZIU_CONTROL 9 289*4882a593Smuzhiyun #define ETYPE_NEXT_PRECISE_STACK_OFL 10 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* Kerenl reserves software ID */ 292*4882a593Smuzhiyun #define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to 293*4882a593Smuzhiyun * raise interrupt level for debug exception 294*4882a593Smuzhiyun */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /****************************************************************************** 297*4882a593Smuzhiyun * ir8: MERR (Machine Error Log Register) 298*4882a593Smuzhiyun *****************************************************************************/ 299*4882a593Smuzhiyun /* bit 0:30 reserved */ 300*4882a593Smuzhiyun #define MERR_offBUSERR 31 /* Bus error caused by a load insn */ 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR ) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /****************************************************************************** 305*4882a593Smuzhiyun * ir9: IPC (Interruption Program Counter Register) 306*4882a593Smuzhiyun * ir10: P_IPC (Previous IPC Register) 307*4882a593Smuzhiyun * ir11: OIPC (Overflow Interruption Program Counter Register) 308*4882a593Smuzhiyun *****************************************************************************/ 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* This is the shadow stack register of the Program Counter */ 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun /****************************************************************************** 313*4882a593Smuzhiyun * ir12: P_P0 (Previous P0 Register) 314*4882a593Smuzhiyun * ir13: P_P1 (Previous P1 Register) 315*4882a593Smuzhiyun *****************************************************************************/ 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* These are shadow registers of $p0 and $p1 */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /****************************************************************************** 320*4882a593Smuzhiyun * ir14: INT_MASK (Interruption Masking Register) 321*4882a593Smuzhiyun *****************************************************************************/ 322*4882a593Smuzhiyun #define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */ 323*4882a593Smuzhiyun #define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */ 324*4882a593Smuzhiyun #define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */ 325*4882a593Smuzhiyun #define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */ 326*4882a593Smuzhiyun #define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */ 327*4882a593Smuzhiyun #define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */ 328*4882a593Smuzhiyun /* bit 6:15 reserved */ 329*4882a593Smuzhiyun #define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */ 330*4882a593Smuzhiyun /* bit 17:29 reserved */ 331*4882a593Smuzhiyun #define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */ 332*4882a593Smuzhiyun #define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */ 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun #define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM ) 335*4882a593Smuzhiyun #define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM ) 336*4882a593Smuzhiyun #define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM ) 337*4882a593Smuzhiyun #define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM ) 338*4882a593Smuzhiyun #define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM ) 339*4882a593Smuzhiyun #define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM ) 340*4882a593Smuzhiyun #define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM ) 341*4882a593Smuzhiyun #define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE ) 342*4882a593Smuzhiyun #define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM ) 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define INT_MASK_INITAIAL_VAL (INT_MASK_mskDSSIM|INT_MASK_mskIDIVZE) 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /****************************************************************************** 347*4882a593Smuzhiyun * ir15: INT_PEND (Interrupt Pending Register) 348*4882a593Smuzhiyun *****************************************************************************/ 349*4882a593Smuzhiyun #define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */ 350*4882a593Smuzhiyun #define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */ 351*4882a593Smuzhiyun #define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */ 352*4882a593Smuzhiyun #define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */ 353*4882a593Smuzhiyun #define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */ 354*4882a593Smuzhiyun #define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */ 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */ 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun /* bit 6:15 reserved */ 359*4882a593Smuzhiyun #define INT_PEND_offSWI 16 /* Software Interrupt pending bit */ 360*4882a593Smuzhiyun /* bit 17:31 reserved */ 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun #define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I ) 363*4882a593Smuzhiyun #define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I ) 364*4882a593Smuzhiyun #define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I ) 365*4882a593Smuzhiyun #define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I ) 366*4882a593Smuzhiyun #define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I ) 367*4882a593Smuzhiyun #define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I ) 368*4882a593Smuzhiyun #define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL ) 369*4882a593Smuzhiyun #define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI ) 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /****************************************************************************** 372*4882a593Smuzhiyun * mr0: MMU_CTL (MMU Control Register) 373*4882a593Smuzhiyun *****************************************************************************/ 374*4882a593Smuzhiyun #define MMU_CTL_offD 0 /* Default minimum page size */ 375*4882a593Smuzhiyun #define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */ 376*4882a593Smuzhiyun #define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */ 377*4882a593Smuzhiyun #define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */ 378*4882a593Smuzhiyun #define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */ 379*4882a593Smuzhiyun #define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */ 380*4882a593Smuzhiyun #define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */ 381*4882a593Smuzhiyun #define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */ 382*4882a593Smuzhiyun #define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */ 383*4882a593Smuzhiyun #define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */ 384*4882a593Smuzhiyun #define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */ 385*4882a593Smuzhiyun #define MMU_CTL_offUNA 23 /* Unaligned access */ 386*4882a593Smuzhiyun /* bit 24:31 reserved */ 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD ) 389*4882a593Smuzhiyun #define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 ) 390*4882a593Smuzhiyun #define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 ) 391*4882a593Smuzhiyun #define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 ) 392*4882a593Smuzhiyun #define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 ) 393*4882a593Smuzhiyun #define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK ) 394*4882a593Smuzhiyun #define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU ) 395*4882a593Smuzhiyun #define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 ) 396*4882a593Smuzhiyun #define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 ) 397*4882a593Smuzhiyun #define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 ) 398*4882a593Smuzhiyun #define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 ) 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun #define MMU_CTL_D4KB 0 401*4882a593Smuzhiyun #define MMU_CTL_D8KB 1 402*4882a593Smuzhiyun #define MMU_CTL_UNA ( 0x1 << MMU_CTL_offUNA ) 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun #define MMU_CTL_CACHEABLE_NON 0 405*4882a593Smuzhiyun #define MMU_CTL_CACHEABLE_WB 2 406*4882a593Smuzhiyun #define MMU_CTL_CACHEABLE_WT 3 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /****************************************************************************** 409*4882a593Smuzhiyun * mr1: L1_PPTB (L1 Physical Page Table Base Register) 410*4882a593Smuzhiyun *****************************************************************************/ 411*4882a593Smuzhiyun #define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */ 412*4882a593Smuzhiyun /* bit 1:11 reserved */ 413*4882a593Smuzhiyun #define L1_PPTB_offBASE 12 /* First level physical page table base address */ 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV ) 416*4882a593Smuzhiyun #define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE ) 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /****************************************************************************** 419*4882a593Smuzhiyun * mr2: TLB_VPN (TLB Access VPN Register) 420*4882a593Smuzhiyun *****************************************************************************/ 421*4882a593Smuzhiyun /* bit 0:11 reserved */ 422*4882a593Smuzhiyun #define TLB_VPN_offVPN 12 /* Virtual Page Number */ 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun #define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN ) 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun /****************************************************************************** 427*4882a593Smuzhiyun * mr3: TLB_DATA (TLB Access Data Register) 428*4882a593Smuzhiyun *****************************************************************************/ 429*4882a593Smuzhiyun #define TLB_DATA_offV 0 /* PTE is valid and present */ 430*4882a593Smuzhiyun #define TLB_DATA_offM 1 /* Page read/write access privilege */ 431*4882a593Smuzhiyun #define TLB_DATA_offD 4 /* Dirty bit */ 432*4882a593Smuzhiyun #define TLB_DATA_offX 5 /* Executable bit */ 433*4882a593Smuzhiyun #define TLB_DATA_offA 6 /* Access bit */ 434*4882a593Smuzhiyun #define TLB_DATA_offG 7 /* Global page (shared across contexts) */ 435*4882a593Smuzhiyun #define TLB_DATA_offC 8 /* Cacheability atribute */ 436*4882a593Smuzhiyun /* bit 11:11 reserved */ 437*4882a593Smuzhiyun #define TLB_DATA_offPPN 12 /* Phisical Page Number */ 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun #define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV ) 440*4882a593Smuzhiyun #define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM ) 441*4882a593Smuzhiyun #define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD ) 442*4882a593Smuzhiyun #define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX ) 443*4882a593Smuzhiyun #define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA ) 444*4882a593Smuzhiyun #define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG ) 445*4882a593Smuzhiyun #define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC ) 446*4882a593Smuzhiyun #define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN ) 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 449*4882a593Smuzhiyun #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC) 450*4882a593Smuzhiyun #else 451*4882a593Smuzhiyun #define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC)) 452*4882a593Smuzhiyun #endif 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun /****************************************************************************** 455*4882a593Smuzhiyun * mr4: TLB_MISC (TLB Access Misc Register) 456*4882a593Smuzhiyun *****************************************************************************/ 457*4882a593Smuzhiyun #define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */ 458*4882a593Smuzhiyun #define TLB_MISC_offCID 4 /* Context id */ 459*4882a593Smuzhiyun /* bit 13:31 reserved */ 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun #define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ ) 462*4882a593Smuzhiyun #define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID ) 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun /****************************************************************************** 465*4882a593Smuzhiyun * mr5: VLPT_IDX (Virtual Linear Page Table Index Register) 466*4882a593Smuzhiyun *****************************************************************************/ 467*4882a593Smuzhiyun #define VLPT_IDX_offZERO 0 /* Always 0 */ 468*4882a593Smuzhiyun #define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */ 469*4882a593Smuzhiyun #define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */ 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun #define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO ) 472*4882a593Smuzhiyun #define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN ) 473*4882a593Smuzhiyun #define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB ) 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun /****************************************************************************** 476*4882a593Smuzhiyun * mr6: ILMB (Instruction Local Memory Base Register) 477*4882a593Smuzhiyun *****************************************************************************/ 478*4882a593Smuzhiyun #define ILMB_offIEN 0 /* Enable ILM */ 479*4882a593Smuzhiyun #define ILMB_offILMSZ 1 /* Size of ILM */ 480*4882a593Smuzhiyun /* bit 5:19 reserved */ 481*4882a593Smuzhiyun #define ILMB_offIBPA 20 /* Base PA of ILM */ 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #define ILMB_mskIEN ( 0x1 << ILMB_offIEN ) 484*4882a593Smuzhiyun #define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ ) 485*4882a593Smuzhiyun #define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA ) 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun /****************************************************************************** 488*4882a593Smuzhiyun * mr7: DLMB (Data Local Memory Base Register) 489*4882a593Smuzhiyun *****************************************************************************/ 490*4882a593Smuzhiyun #define DLMB_offDEN 0 /* Enable DLM */ 491*4882a593Smuzhiyun #define DLMB_offDLMSZ 1 /* Size of DLM */ 492*4882a593Smuzhiyun #define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */ 493*4882a593Smuzhiyun #define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */ 494*4882a593Smuzhiyun /* bit 7:19 reserved */ 495*4882a593Smuzhiyun #define DLMB_offDBPA 20 /* Base PA of DLM */ 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun #define DLMB_mskDEN ( 0x1 << DLMB_offDEN ) 498*4882a593Smuzhiyun #define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ ) 499*4882a593Smuzhiyun #define DLMB_mskDBM ( 0x1 << DLMB_offDBM ) 500*4882a593Smuzhiyun #define DLMB_mskDBB ( 0x1 << DLMB_offDBB ) 501*4882a593Smuzhiyun #define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA ) 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /****************************************************************************** 504*4882a593Smuzhiyun * mr8: CACHE_CTL (Cache Control Register) 505*4882a593Smuzhiyun *****************************************************************************/ 506*4882a593Smuzhiyun #define CACHE_CTL_offIC_EN 0 /* Enable I-cache */ 507*4882a593Smuzhiyun #define CACHE_CTL_offDC_EN 1 /* Enable D-cache */ 508*4882a593Smuzhiyun #define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */ 509*4882a593Smuzhiyun #define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */ 510*4882a593Smuzhiyun #define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */ 511*4882a593Smuzhiyun #define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */ 512*4882a593Smuzhiyun /* bit 6:31 reserved */ 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN ) 515*4882a593Smuzhiyun #define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN ) 516*4882a593Smuzhiyun #define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK ) 517*4882a593Smuzhiyun #define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK ) 518*4882a593Smuzhiyun #define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF ) 519*4882a593Smuzhiyun #define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW ) 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun /****************************************************************************** 522*4882a593Smuzhiyun * mr9: HSMP_SADDR (High Speed Memory Port Starting Address) 523*4882a593Smuzhiyun *****************************************************************************/ 524*4882a593Smuzhiyun #define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */ 525*4882a593Smuzhiyun /* bit 1:19 reserved */ 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun #define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */ 528*4882a593Smuzhiyun #define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */ 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun #define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN ) 531*4882a593Smuzhiyun #define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE ) 532*4882a593Smuzhiyun #define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR ) 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun /****************************************************************************** 535*4882a593Smuzhiyun * mr10: HSMP_EADDR (High Speed Memory Port Ending Address) 536*4882a593Smuzhiyun *****************************************************************************/ 537*4882a593Smuzhiyun /* bit 0:19 reserved */ 538*4882a593Smuzhiyun #define HSMP_EADDR_offEADDR 20 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun #define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR ) 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun /****************************************************************************** 543*4882a593Smuzhiyun * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register) 544*4882a593Smuzhiyun *****************************************************************************/ 545*4882a593Smuzhiyun #define BPC_offWP 0 /* Configuration of BPAn */ 546*4882a593Smuzhiyun #define BPC_offEL 1 /* Enable BPAn */ 547*4882a593Smuzhiyun #define BPC_offS 2 /* Data address comparison for a store instruction */ 548*4882a593Smuzhiyun #define BPC_offP 3 /* Compared data address is PA */ 549*4882a593Smuzhiyun #define BPC_offC 4 /* CID value is compared with the BPCIDn register */ 550*4882a593Smuzhiyun #define BPC_offBE0 5 /* Enable byte mask for the comparison with register */ 551*4882a593Smuzhiyun #define BPC_offBE1 6 /* Enable byte mask for the comparison with register */ 552*4882a593Smuzhiyun #define BPC_offBE2 7 /* Enable byte mask for the comparison with register */ 553*4882a593Smuzhiyun #define BPC_offBE3 8 /* Enable byte mask for the comparison with register */ 554*4882a593Smuzhiyun #define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */ 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun #define BPC_mskWP ( 0x1 << BPC_offWP ) 557*4882a593Smuzhiyun #define BPC_mskEL ( 0x1 << BPC_offEL ) 558*4882a593Smuzhiyun #define BPC_mskS ( 0x1 << BPC_offS ) 559*4882a593Smuzhiyun #define BPC_mskP ( 0x1 << BPC_offP ) 560*4882a593Smuzhiyun #define BPC_mskC ( 0x1 << BPC_offC ) 561*4882a593Smuzhiyun #define BPC_mskBE0 ( 0x1 << BPC_offBE0 ) 562*4882a593Smuzhiyun #define BPC_mskBE1 ( 0x1 << BPC_offBE1 ) 563*4882a593Smuzhiyun #define BPC_mskBE2 ( 0x1 << BPC_offBE2 ) 564*4882a593Smuzhiyun #define BPC_mskBE3 ( 0x1 << BPC_offBE3 ) 565*4882a593Smuzhiyun #define BPC_mskT ( 0x1 << BPC_offT ) 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun /****************************************************************************** 568*4882a593Smuzhiyun * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register) 569*4882a593Smuzhiyun *****************************************************************************/ 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun /* These registers contain break point address */ 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun /****************************************************************************** 574*4882a593Smuzhiyun * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register) 575*4882a593Smuzhiyun *****************************************************************************/ 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /* These registerd contain the address comparison mask for the BPAn register */ 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun /****************************************************************************** 580*4882a593Smuzhiyun * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register 581*4882a593Smuzhiyun *****************************************************************************/ 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun /* The BPVn register contains the data value that will be compared with the 584*4882a593Smuzhiyun * incoming load/store data value */ 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun /****************************************************************************** 587*4882a593Smuzhiyun * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register) 588*4882a593Smuzhiyun *****************************************************************************/ 589*4882a593Smuzhiyun #define BPCID_offCID 0 /* CID that will be compared with a process's CID */ 590*4882a593Smuzhiyun /* bit 9:31 reserved */ 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun #define BPCID_mskCID ( 0x1FF << BPCID_offCID ) 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun /****************************************************************************** 595*4882a593Smuzhiyun * dr40: EDM_CFG (EDM Configuration Register) 596*4882a593Smuzhiyun *****************************************************************************/ 597*4882a593Smuzhiyun #define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */ 598*4882a593Smuzhiyun #define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */ 599*4882a593Smuzhiyun /* bit 4:15 reserved */ 600*4882a593Smuzhiyun #define EDM_CFG_offVER 16 /* EDM version */ 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun #define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC ) 603*4882a593Smuzhiyun #define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU ) 604*4882a593Smuzhiyun #define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER ) 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun /****************************************************************************** 607*4882a593Smuzhiyun * dr41: EDMSW (EDM Status Word) 608*4882a593Smuzhiyun *****************************************************************************/ 609*4882a593Smuzhiyun #define EDMSW_offWV 0 /* Write Valid */ 610*4882a593Smuzhiyun #define EDMSW_offRV 1 /* Read Valid */ 611*4882a593Smuzhiyun #define EDMSW_offDE 2 /* Debug exception has occurred for this core */ 612*4882a593Smuzhiyun /* bit 3:31 reserved */ 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun #define EDMSW_mskWV ( 0x1 << EDMSW_offWV ) 615*4882a593Smuzhiyun #define EDMSW_mskRV ( 0x1 << EDMSW_offRV ) 616*4882a593Smuzhiyun #define EDMSW_mskDE ( 0x1 << EDMSW_offDE ) 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun /****************************************************************************** 619*4882a593Smuzhiyun * dr42: EDM_CTL (EDM Control Register) 620*4882a593Smuzhiyun *****************************************************************************/ 621*4882a593Smuzhiyun /* bit 0:30 reserved */ 622*4882a593Smuzhiyun #define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */ 623*4882a593Smuzhiyun #define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */ 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun #define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE ) 626*4882a593Smuzhiyun #define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL ) 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /****************************************************************************** 629*4882a593Smuzhiyun * dr43: EDM_DTR (EDM Data Transfer Register) 630*4882a593Smuzhiyun *****************************************************************************/ 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun /* This is used to exchange data between the embedded EDM logic 633*4882a593Smuzhiyun * and the processor core */ 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun /****************************************************************************** 636*4882a593Smuzhiyun * dr44: BPMTC (Breakpoint Match Trigger Counter Register) 637*4882a593Smuzhiyun *****************************************************************************/ 638*4882a593Smuzhiyun #define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */ 639*4882a593Smuzhiyun /* bit 16:31 reserved */ 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun #define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC ) 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun /****************************************************************************** 644*4882a593Smuzhiyun * dr45: DIMBR (Debug Instruction Memory Base Register) 645*4882a593Smuzhiyun *****************************************************************************/ 646*4882a593Smuzhiyun /* bit 0:11 reserved */ 647*4882a593Smuzhiyun #define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */ 648*4882a593Smuzhiyun #define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB ) 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun /****************************************************************************** 651*4882a593Smuzhiyun * dr46: TECR0(Trigger Event Control register 0) 652*4882a593Smuzhiyun * dr47: TECR1 (Trigger Event Control register 1) 653*4882a593Smuzhiyun *****************************************************************************/ 654*4882a593Smuzhiyun #define TECR_offBP 0 /* Controld which BP is used as a trigger source */ 655*4882a593Smuzhiyun #define TECR_offNMI 8 /* Use NMI as a trigger source */ 656*4882a593Smuzhiyun #define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */ 657*4882a593Smuzhiyun #define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */ 658*4882a593Smuzhiyun #define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */ 659*4882a593Smuzhiyun #define TECR_offDBG 17 /* Enable debug exception as a trigger source */ 660*4882a593Smuzhiyun #define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */ 661*4882a593Smuzhiyun #define TECR_offE 19 /* An exception is used as a trigger source */ 662*4882a593Smuzhiyun /* bit 20:30 reserved */ 663*4882a593Smuzhiyun #define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */ 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun #define TECR_mskBP ( 0xFF << TECR_offBP ) 666*4882a593Smuzhiyun #define TECR_mskNMI ( 0x1 << TECR_offBNMI ) 667*4882a593Smuzhiyun #define TECR_mskHWINT ( 0x3F << TECR_offBHWINT ) 668*4882a593Smuzhiyun #define TECR_mskEVIC ( 0x1 << TECR_offBEVIC ) 669*4882a593Smuzhiyun #define TECR_mskSYS ( 0x1 << TECR_offBSYS ) 670*4882a593Smuzhiyun #define TECR_mskDBG ( 0x1 << TECR_offBDBG ) 671*4882a593Smuzhiyun #define TECR_mskMRE ( 0x1 << TECR_offBMRE ) 672*4882a593Smuzhiyun #define TECR_mskE ( 0x1 << TECR_offE ) 673*4882a593Smuzhiyun #define TECR_mskL ( 0x1 << TECR_offL ) 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun /****************************************************************************** 676*4882a593Smuzhiyun * pfr0-2: PFMC0-2 (Performance Counter Register 0-2) 677*4882a593Smuzhiyun *****************************************************************************/ 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun /* These registers contains performance event count */ 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun /****************************************************************************** 682*4882a593Smuzhiyun * pfr3: PFM_CTL (Performance Counter Control Register) 683*4882a593Smuzhiyun *****************************************************************************/ 684*4882a593Smuzhiyun #define PFM_CTL_offEN0 0 /* Enable PFMC0 */ 685*4882a593Smuzhiyun #define PFM_CTL_offEN1 1 /* Enable PFMC1 */ 686*4882a593Smuzhiyun #define PFM_CTL_offEN2 2 /* Enable PFMC2 */ 687*4882a593Smuzhiyun #define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */ 688*4882a593Smuzhiyun #define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */ 689*4882a593Smuzhiyun #define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */ 690*4882a593Smuzhiyun #define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */ 691*4882a593Smuzhiyun #define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */ 692*4882a593Smuzhiyun #define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */ 693*4882a593Smuzhiyun #define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */ 694*4882a593Smuzhiyun #define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */ 695*4882a593Smuzhiyun #define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */ 696*4882a593Smuzhiyun #define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */ 697*4882a593Smuzhiyun #define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */ 698*4882a593Smuzhiyun #define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */ 699*4882a593Smuzhiyun #define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */ 700*4882a593Smuzhiyun #define PFM_CTL_offSEL1 16 /* The event selection for PFMC1 */ 701*4882a593Smuzhiyun #define PFM_CTL_offSEL2 22 /* The event selection for PFMC2 */ 702*4882a593Smuzhiyun /* bit 28:31 reserved */ 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun #define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 ) 705*4882a593Smuzhiyun #define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 ) 706*4882a593Smuzhiyun #define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 ) 707*4882a593Smuzhiyun #define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 ) 708*4882a593Smuzhiyun #define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 ) 709*4882a593Smuzhiyun #define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 ) 710*4882a593Smuzhiyun #define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 ) 711*4882a593Smuzhiyun #define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 ) 712*4882a593Smuzhiyun #define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 ) 713*4882a593Smuzhiyun #define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 ) 714*4882a593Smuzhiyun #define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 ) 715*4882a593Smuzhiyun #define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 ) 716*4882a593Smuzhiyun #define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 ) 717*4882a593Smuzhiyun #define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 ) 718*4882a593Smuzhiyun #define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 ) 719*4882a593Smuzhiyun #define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 ) 720*4882a593Smuzhiyun #define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 ) 721*4882a593Smuzhiyun #define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 ) 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun /****************************************************************************** 724*4882a593Smuzhiyun * SDZ_CTL (Structure Downsizing Control Register) 725*4882a593Smuzhiyun *****************************************************************************/ 726*4882a593Smuzhiyun #define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */ 727*4882a593Smuzhiyun #define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */ 728*4882a593Smuzhiyun #define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */ 729*4882a593Smuzhiyun #define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */ 730*4882a593Smuzhiyun /* bit 12:31 reserved */ 731*4882a593Smuzhiyun #define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ ) 732*4882a593Smuzhiyun #define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ ) 733*4882a593Smuzhiyun #define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ ) 734*4882a593Smuzhiyun #define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ ) 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun /****************************************************************************** 737*4882a593Smuzhiyun * N13MISC_CTL (N13 Miscellaneous Control Register) 738*4882a593Smuzhiyun *****************************************************************************/ 739*4882a593Smuzhiyun #define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */ 740*4882a593Smuzhiyun #define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */ 741*4882a593Smuzhiyun #define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */ 742*4882a593Smuzhiyun #define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */ 743*4882a593Smuzhiyun #define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */ 744*4882a593Smuzhiyun /* bit 6, 9:31 reserved */ 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun #define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB ) 747*4882a593Smuzhiyun #define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP ) 748*4882a593Smuzhiyun #define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF ) 749*4882a593Smuzhiyun #define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN ) 750*4882a593Smuzhiyun #define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE ) 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun #ifdef CONFIG_HW_PRE 753*4882a593Smuzhiyun #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN) 754*4882a593Smuzhiyun #else 755*4882a593Smuzhiyun #define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN) 756*4882a593Smuzhiyun #endif 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun /****************************************************************************** 759*4882a593Smuzhiyun * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers) 760*4882a593Smuzhiyun *****************************************************************************/ 761*4882a593Smuzhiyun #define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */ 762*4882a593Smuzhiyun #define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */ 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun #define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN ) 765*4882a593Smuzhiyun #define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN ) 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun /****************************************************************************** 768*4882a593Smuzhiyun * dmar0: DMA_CFG (DMA Configuration Register) 769*4882a593Smuzhiyun *****************************************************************************/ 770*4882a593Smuzhiyun #define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */ 771*4882a593Smuzhiyun #define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */ 772*4882a593Smuzhiyun #define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */ 773*4882a593Smuzhiyun /* bit 4:15 reserved */ 774*4882a593Smuzhiyun #define DMA_CFG_offVER 16 /* DMA architecture and implementation version */ 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun #define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN ) 777*4882a593Smuzhiyun #define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA ) 778*4882a593Smuzhiyun #define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET ) 779*4882a593Smuzhiyun #define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER ) 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun /****************************************************************************** 782*4882a593Smuzhiyun * dmar1: DMA_GCSW (DMA Global Control and Status Word Register) 783*4882a593Smuzhiyun *****************************************************************************/ 784*4882a593Smuzhiyun #define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */ 785*4882a593Smuzhiyun #define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */ 786*4882a593Smuzhiyun /* bit 6:11 reserved */ 787*4882a593Smuzhiyun #define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */ 788*4882a593Smuzhiyun #define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */ 789*4882a593Smuzhiyun /* bit 14:30 reserved */ 790*4882a593Smuzhiyun #define DMA_GCSW_offEN 31 /* Enable DMA engine */ 791*4882a593Smuzhiyun 792*4882a593Smuzhiyun #define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT ) 793*4882a593Smuzhiyun #define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT ) 794*4882a593Smuzhiyun #define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT ) 795*4882a593Smuzhiyun #define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT ) 796*4882a593Smuzhiyun #define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN ) 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun /****************************************************************************** 799*4882a593Smuzhiyun * dmar2: DMA_CHNSEL (DMA Channel Selection Register) 800*4882a593Smuzhiyun *****************************************************************************/ 801*4882a593Smuzhiyun #define DMA_CHNSEL_offCHAN 0 /* Selected channel number */ 802*4882a593Smuzhiyun /* bit 2:31 reserved */ 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun #define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN ) 805*4882a593Smuzhiyun 806*4882a593Smuzhiyun /****************************************************************************** 807*4882a593Smuzhiyun * dmar3: DMA_ACT (DMA Action Register) 808*4882a593Smuzhiyun *****************************************************************************/ 809*4882a593Smuzhiyun #define DMA_ACT_offACMD 0 /* DMA Action Command */ 810*4882a593Smuzhiyun /* bit 2:31 reserved */ 811*4882a593Smuzhiyun #define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD ) 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun /****************************************************************************** 814*4882a593Smuzhiyun * dmar4: DMA_SETUP (DMA Setup Register) 815*4882a593Smuzhiyun *****************************************************************************/ 816*4882a593Smuzhiyun #define DMA_SETUP_offLM 0 /* Local Memory Selection */ 817*4882a593Smuzhiyun #define DMA_SETUP_offTDIR 1 /* Transfer Direction */ 818*4882a593Smuzhiyun #define DMA_SETUP_offTES 2 /* Transfer Element Size */ 819*4882a593Smuzhiyun #define DMA_SETUP_offESTR 4 /* External memory transfer Stride */ 820*4882a593Smuzhiyun #define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */ 821*4882a593Smuzhiyun #define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */ 822*4882a593Smuzhiyun #define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */ 823*4882a593Smuzhiyun #define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */ 824*4882a593Smuzhiyun #define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */ 825*4882a593Smuzhiyun #define DMA_SETUP_offCOA 21 /* Transfer Coalescable */ 826*4882a593Smuzhiyun /* bit 22:31 reserved */ 827*4882a593Smuzhiyun 828*4882a593Smuzhiyun #define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM ) 829*4882a593Smuzhiyun #define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR ) 830*4882a593Smuzhiyun #define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES ) 831*4882a593Smuzhiyun #define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR ) 832*4882a593Smuzhiyun #define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE ) 833*4882a593Smuzhiyun #define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE ) 834*4882a593Smuzhiyun #define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE ) 835*4882a593Smuzhiyun #define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE ) 836*4882a593Smuzhiyun #define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE ) 837*4882a593Smuzhiyun #define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA ) 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun /****************************************************************************** 840*4882a593Smuzhiyun * dmar5: DMA_ISADDR (DMA Internal Start Address Register) 841*4882a593Smuzhiyun *****************************************************************************/ 842*4882a593Smuzhiyun #define DMA_ISADDR_offISADDR 0 /* Internal Start Address */ 843*4882a593Smuzhiyun /* bit 20:31 reserved */ 844*4882a593Smuzhiyun #define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR ) 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun /****************************************************************************** 847*4882a593Smuzhiyun * dmar6: DMA_ESADDR (DMA External Start Address Register) 848*4882a593Smuzhiyun *****************************************************************************/ 849*4882a593Smuzhiyun /* This register holds External Start Address */ 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun /****************************************************************************** 852*4882a593Smuzhiyun * dmar7: DMA_TCNT (DMA Transfer Element Count Register) 853*4882a593Smuzhiyun *****************************************************************************/ 854*4882a593Smuzhiyun #define DMA_TCNT_offTCNT 0 /* DMA transfer element count */ 855*4882a593Smuzhiyun /* bit 18:31 reserved */ 856*4882a593Smuzhiyun #define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT ) 857*4882a593Smuzhiyun 858*4882a593Smuzhiyun /****************************************************************************** 859*4882a593Smuzhiyun * dmar8: DMA_STATUS (DMA Status Register) 860*4882a593Smuzhiyun *****************************************************************************/ 861*4882a593Smuzhiyun #define DMA_STATUS_offSTAT 0 /* DMA channel state */ 862*4882a593Smuzhiyun #define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */ 863*4882a593Smuzhiyun #define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */ 864*4882a593Smuzhiyun #define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */ 865*4882a593Smuzhiyun #define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */ 866*4882a593Smuzhiyun #define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */ 867*4882a593Smuzhiyun #define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */ 868*4882a593Smuzhiyun #define DMA_STATUS_offESUP 9 /* DMA setup error */ 869*4882a593Smuzhiyun /* bit 10:31 reserved */ 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun #define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT ) 872*4882a593Smuzhiyun #define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA ) 873*4882a593Smuzhiyun #define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR ) 874*4882a593Smuzhiyun #define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA ) 875*4882a593Smuzhiyun #define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA ) 876*4882a593Smuzhiyun #define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR ) 877*4882a593Smuzhiyun #define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS ) 878*4882a593Smuzhiyun #define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP ) 879*4882a593Smuzhiyun 880*4882a593Smuzhiyun /****************************************************************************** 881*4882a593Smuzhiyun * dmar9: DMA_2DSET (DMA 2D Setup Register) 882*4882a593Smuzhiyun *****************************************************************************/ 883*4882a593Smuzhiyun #define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */ 884*4882a593Smuzhiyun #define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */ 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun #define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR ) 887*4882a593Smuzhiyun #define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT ) 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun /****************************************************************************** 890*4882a593Smuzhiyun * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register) 891*4882a593Smuzhiyun *****************************************************************************/ 892*4882a593Smuzhiyun #define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */ 893*4882a593Smuzhiyun /* bit 16:31 reserved */ 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun #define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT ) 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun /****************************************************************************** 898*4882a593Smuzhiyun * fpcsr: FPCSR (Floating-Point Control Status Register) 899*4882a593Smuzhiyun *****************************************************************************/ 900*4882a593Smuzhiyun #define FPCSR_offRM 0 901*4882a593Smuzhiyun #define FPCSR_offIVO 2 902*4882a593Smuzhiyun #define FPCSR_offDBZ 3 903*4882a593Smuzhiyun #define FPCSR_offOVF 4 904*4882a593Smuzhiyun #define FPCSR_offUDF 5 905*4882a593Smuzhiyun #define FPCSR_offIEX 6 906*4882a593Smuzhiyun #define FPCSR_offIVOE 7 907*4882a593Smuzhiyun #define FPCSR_offDBZE 8 908*4882a593Smuzhiyun #define FPCSR_offOVFE 9 909*4882a593Smuzhiyun #define FPCSR_offUDFE 10 910*4882a593Smuzhiyun #define FPCSR_offIEXE 11 911*4882a593Smuzhiyun #define FPCSR_offDNZ 12 912*4882a593Smuzhiyun #define FPCSR_offIVOT 13 913*4882a593Smuzhiyun #define FPCSR_offDBZT 14 914*4882a593Smuzhiyun #define FPCSR_offOVFT 15 915*4882a593Smuzhiyun #define FPCSR_offUDFT 16 916*4882a593Smuzhiyun #define FPCSR_offIEXT 17 917*4882a593Smuzhiyun #define FPCSR_offDNIT 18 918*4882a593Smuzhiyun #define FPCSR_offRIT 19 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun #define FPCSR_mskRM ( 0x3 << FPCSR_offRM ) 921*4882a593Smuzhiyun #define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO ) 922*4882a593Smuzhiyun #define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ ) 923*4882a593Smuzhiyun #define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF ) 924*4882a593Smuzhiyun #define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF ) 925*4882a593Smuzhiyun #define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX ) 926*4882a593Smuzhiyun #define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE ) 927*4882a593Smuzhiyun #define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE ) 928*4882a593Smuzhiyun #define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE ) 929*4882a593Smuzhiyun #define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE ) 930*4882a593Smuzhiyun #define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE ) 931*4882a593Smuzhiyun #define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ ) 932*4882a593Smuzhiyun #define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT ) 933*4882a593Smuzhiyun #define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT ) 934*4882a593Smuzhiyun #define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT ) 935*4882a593Smuzhiyun #define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT ) 936*4882a593Smuzhiyun #define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT ) 937*4882a593Smuzhiyun #define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT ) 938*4882a593Smuzhiyun #define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT ) 939*4882a593Smuzhiyun #define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX) 940*4882a593Smuzhiyun #define FPCSR_mskALLE_NO_UDF_IEXE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE) 941*4882a593Smuzhiyun #define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE) 942*4882a593Smuzhiyun #define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT) 943*4882a593Smuzhiyun 944*4882a593Smuzhiyun /****************************************************************************** 945*4882a593Smuzhiyun * fpcfg: FPCFG (Floating-Point Configuration Register) 946*4882a593Smuzhiyun *****************************************************************************/ 947*4882a593Smuzhiyun #define FPCFG_offSP 0 948*4882a593Smuzhiyun #define FPCFG_offDP 1 949*4882a593Smuzhiyun #define FPCFG_offFREG 2 950*4882a593Smuzhiyun #define FPCFG_offFMA 4 951*4882a593Smuzhiyun #define FPCFG_offIMVER 22 952*4882a593Smuzhiyun #define FPCFG_offAVER 27 953*4882a593Smuzhiyun 954*4882a593Smuzhiyun #define FPCFG_mskSP ( 0x1 << FPCFG_offSP ) 955*4882a593Smuzhiyun #define FPCFG_mskDP ( 0x1 << FPCFG_offDP ) 956*4882a593Smuzhiyun #define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG ) 957*4882a593Smuzhiyun #define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA ) 958*4882a593Smuzhiyun #define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER ) 959*4882a593Smuzhiyun #define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER ) 960*4882a593Smuzhiyun 961*4882a593Smuzhiyun /* 8 Single precision or 4 double precision registers are available */ 962*4882a593Smuzhiyun #define SP8_DP4_reg 0 963*4882a593Smuzhiyun /* 16 Single precision or 8 double precision registers are available */ 964*4882a593Smuzhiyun #define SP16_DP8_reg 1 965*4882a593Smuzhiyun /* 32 Single precision or 16 double precision registers are available */ 966*4882a593Smuzhiyun #define SP32_DP16_reg 2 967*4882a593Smuzhiyun /* 32 Single precision or 32 double precision registers are available */ 968*4882a593Smuzhiyun #define SP32_DP32_reg 3 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun /****************************************************************************** 971*4882a593Smuzhiyun * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register) 972*4882a593Smuzhiyun *****************************************************************************/ 973*4882a593Smuzhiyun #define FUCOP_CTL_offCP0EN 0 974*4882a593Smuzhiyun #define FUCOP_CTL_offCP1EN 1 975*4882a593Smuzhiyun #define FUCOP_CTL_offCP2EN 2 976*4882a593Smuzhiyun #define FUCOP_CTL_offCP3EN 3 977*4882a593Smuzhiyun #define FUCOP_CTL_offAUEN 31 978*4882a593Smuzhiyun 979*4882a593Smuzhiyun #define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN ) 980*4882a593Smuzhiyun #define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN ) 981*4882a593Smuzhiyun #define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN ) 982*4882a593Smuzhiyun #define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN ) 983*4882a593Smuzhiyun #define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN ) 984*4882a593Smuzhiyun 985*4882a593Smuzhiyun #endif /* __NDS32_BITFIELD_H__ */ 986