1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun compatible = "andestech,ae3xx"; 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun interrupt-parent = <&intc>; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun chosen { 9*4882a593Smuzhiyun stdout-path = &serial0; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun memory@0 { 13*4882a593Smuzhiyun device_type = "memory"; 14*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun cpu@0 { 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun compatible = "andestech,n13", "andestech,nds32v3"; 23*4882a593Smuzhiyun reg = <0>; 24*4882a593Smuzhiyun clock-frequency = <60000000>; 25*4882a593Smuzhiyun next-level-cache = <&L2>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun intc: interrupt-controller { 30*4882a593Smuzhiyun compatible = "andestech,ativic32"; 31*4882a593Smuzhiyun #interrupt-cells = <1>; 32*4882a593Smuzhiyun interrupt-controller; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun clock: clk { 36*4882a593Smuzhiyun #clock-cells = <0>; 37*4882a593Smuzhiyun compatible = "fixed-clock"; 38*4882a593Smuzhiyun clock-frequency = <30000000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun apb { 42*4882a593Smuzhiyun compatible = "simple-bus"; 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <1>; 45*4882a593Smuzhiyun ranges; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun serial0: serial@f0300000 { 48*4882a593Smuzhiyun compatible = "andestech,uart16550", "ns16550a"; 49*4882a593Smuzhiyun reg = <0xf0300000 0x1000>; 50*4882a593Smuzhiyun interrupts = <8>; 51*4882a593Smuzhiyun clock-frequency = <14745600>; 52*4882a593Smuzhiyun reg-shift = <2>; 53*4882a593Smuzhiyun reg-offset = <32>; 54*4882a593Smuzhiyun no-loopback-test = <1>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun timer0: timer@f0400000 { 58*4882a593Smuzhiyun compatible = "andestech,atcpit100"; 59*4882a593Smuzhiyun reg = <0xf0400000 0x1000>; 60*4882a593Smuzhiyun interrupts = <2>; 61*4882a593Smuzhiyun clocks = <&clock>; 62*4882a593Smuzhiyun clock-names = "PCLK"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun ahb { 67*4882a593Smuzhiyun compatible = "simple-bus"; 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <1>; 70*4882a593Smuzhiyun ranges; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun L2: cache-controller@e0500000 { 73*4882a593Smuzhiyun compatible = "andestech,atl2c"; 74*4882a593Smuzhiyun reg = <0xe0500000 0x1000>; 75*4882a593Smuzhiyun cache-unified; 76*4882a593Smuzhiyun cache-level = <2>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun mac0: ethernet@e0100000 { 80*4882a593Smuzhiyun compatible = "andestech,atmac100"; 81*4882a593Smuzhiyun reg = <0xe0100000 0x1000>; 82*4882a593Smuzhiyun interrupts = <18>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun pmu { 87*4882a593Smuzhiyun compatible = "andestech,nds32v3-pmu"; 88*4882a593Smuzhiyun interrupts= <13>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91