1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NEC VR4100 series SIU platform device.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007-2008 Yoichi Yuasa <yuasa@linux-mips.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/errno.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/ioport.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/serial_core.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/cpu.h>
15*4882a593Smuzhiyun #include <asm/vr41xx/siu.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static unsigned int siu_type1_ports[SIU_PORTS_MAX] __initdata = {
18*4882a593Smuzhiyun PORT_VR41XX_SIU,
19*4882a593Smuzhiyun PORT_UNKNOWN,
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static struct resource siu_type1_resource[] __initdata = {
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun .start = 0x0c000000,
25*4882a593Smuzhiyun .end = 0x0c00000a,
26*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
27*4882a593Smuzhiyun },
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun .start = SIU_IRQ,
30*4882a593Smuzhiyun .end = SIU_IRQ,
31*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static unsigned int siu_type2_ports[SIU_PORTS_MAX] __initdata = {
36*4882a593Smuzhiyun PORT_VR41XX_SIU,
37*4882a593Smuzhiyun PORT_VR41XX_DSIU,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static struct resource siu_type2_resource[] __initdata = {
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun .start = 0x0f000800,
43*4882a593Smuzhiyun .end = 0x0f00080a,
44*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
45*4882a593Smuzhiyun },
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun .start = 0x0f000820,
48*4882a593Smuzhiyun .end = 0x0f000829,
49*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
50*4882a593Smuzhiyun },
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun .start = SIU_IRQ,
53*4882a593Smuzhiyun .end = SIU_IRQ,
54*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun .start = DSIU_IRQ,
58*4882a593Smuzhiyun .end = DSIU_IRQ,
59*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
vr41xx_siu_add(void)63*4882a593Smuzhiyun static int __init vr41xx_siu_add(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct platform_device *pdev;
66*4882a593Smuzhiyun struct resource *res;
67*4882a593Smuzhiyun unsigned int num;
68*4882a593Smuzhiyun int retval;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun pdev = platform_device_alloc("SIU", -1);
71*4882a593Smuzhiyun if (!pdev)
72*4882a593Smuzhiyun return -ENOMEM;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun switch (current_cpu_type()) {
75*4882a593Smuzhiyun case CPU_VR4111:
76*4882a593Smuzhiyun case CPU_VR4121:
77*4882a593Smuzhiyun pdev->dev.platform_data = siu_type1_ports;
78*4882a593Smuzhiyun res = siu_type1_resource;
79*4882a593Smuzhiyun num = ARRAY_SIZE(siu_type1_resource);
80*4882a593Smuzhiyun break;
81*4882a593Smuzhiyun case CPU_VR4122:
82*4882a593Smuzhiyun case CPU_VR4131:
83*4882a593Smuzhiyun case CPU_VR4133:
84*4882a593Smuzhiyun pdev->dev.platform_data = siu_type2_ports;
85*4882a593Smuzhiyun res = siu_type2_resource;
86*4882a593Smuzhiyun num = ARRAY_SIZE(siu_type2_resource);
87*4882a593Smuzhiyun break;
88*4882a593Smuzhiyun default:
89*4882a593Smuzhiyun retval = -ENODEV;
90*4882a593Smuzhiyun goto err_free_device;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun retval = platform_device_add_resources(pdev, res, num);
94*4882a593Smuzhiyun if (retval)
95*4882a593Smuzhiyun goto err_free_device;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun retval = platform_device_add(pdev);
98*4882a593Smuzhiyun if (retval)
99*4882a593Smuzhiyun goto err_free_device;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun err_free_device:
104*4882a593Smuzhiyun platform_device_put(pdev);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return retval;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun device_initcall(vr41xx_siu_add);
109*4882a593Smuzhiyun
vr41xx_siu_setup(void)110*4882a593Smuzhiyun void __init vr41xx_siu_setup(void)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct uart_port port;
113*4882a593Smuzhiyun struct resource *res;
114*4882a593Smuzhiyun unsigned int *type;
115*4882a593Smuzhiyun int i;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun switch (current_cpu_type()) {
118*4882a593Smuzhiyun case CPU_VR4111:
119*4882a593Smuzhiyun case CPU_VR4121:
120*4882a593Smuzhiyun type = siu_type1_ports;
121*4882a593Smuzhiyun res = siu_type1_resource;
122*4882a593Smuzhiyun break;
123*4882a593Smuzhiyun case CPU_VR4122:
124*4882a593Smuzhiyun case CPU_VR4131:
125*4882a593Smuzhiyun case CPU_VR4133:
126*4882a593Smuzhiyun type = siu_type2_ports;
127*4882a593Smuzhiyun res = siu_type2_resource;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun default:
130*4882a593Smuzhiyun return;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun for (i = 0; i < SIU_PORTS_MAX; i++) {
134*4882a593Smuzhiyun port.line = i;
135*4882a593Smuzhiyun port.type = type[i];
136*4882a593Smuzhiyun if (port.type == PORT_UNKNOWN)
137*4882a593Smuzhiyun break;
138*4882a593Smuzhiyun port.mapbase = res[i].start;
139*4882a593Smuzhiyun port.membase = (unsigned char __iomem *)KSEG1ADDR(res[i].start);
140*4882a593Smuzhiyun vr41xx_siu_early_setup(&port);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun }
143