1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * pmu.c, Power Management Unit routines for NEC VR4100 series.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2003-2007 Yoichi Yuasa <yuasa@linux-mips.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/cpu.h>
8*4882a593Smuzhiyun #include <linux/errno.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/ioport.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/pm.h>
13*4882a593Smuzhiyun #include <linux/sched.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/cacheflush.h>
17*4882a593Smuzhiyun #include <asm/cpu.h>
18*4882a593Smuzhiyun #include <asm/idle.h>
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun #include <asm/processor.h>
21*4882a593Smuzhiyun #include <asm/reboot.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define PMU_TYPE1_BASE 0x0b0000a0UL
24*4882a593Smuzhiyun #define PMU_TYPE1_SIZE 0x0eUL
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define PMU_TYPE2_BASE 0x0f0000c0UL
27*4882a593Smuzhiyun #define PMU_TYPE2_SIZE 0x10UL
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PMUCNT2REG 0x06
30*4882a593Smuzhiyun #define SOFTRST 0x0010
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static void __iomem *pmu_base;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define pmu_read(offset) readw(pmu_base + (offset))
35*4882a593Smuzhiyun #define pmu_write(offset, value) writew((value), pmu_base + (offset))
36*4882a593Smuzhiyun
vr41xx_cpu_wait(void)37*4882a593Smuzhiyun static void __cpuidle vr41xx_cpu_wait(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun local_irq_disable();
40*4882a593Smuzhiyun if (!need_resched())
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * "standby" sets IE bit of the CP0_STATUS to 1.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun __asm__("standby;\n");
45*4882a593Smuzhiyun else
46*4882a593Smuzhiyun local_irq_enable();
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
software_reset(void)49*4882a593Smuzhiyun static inline void software_reset(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun uint16_t pmucnt2;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun switch (current_cpu_type()) {
54*4882a593Smuzhiyun case CPU_VR4122:
55*4882a593Smuzhiyun case CPU_VR4131:
56*4882a593Smuzhiyun case CPU_VR4133:
57*4882a593Smuzhiyun pmucnt2 = pmu_read(PMUCNT2REG);
58*4882a593Smuzhiyun pmucnt2 |= SOFTRST;
59*4882a593Smuzhiyun pmu_write(PMUCNT2REG, pmucnt2);
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun default:
62*4882a593Smuzhiyun set_c0_status(ST0_BEV | ST0_ERL);
63*4882a593Smuzhiyun change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
64*4882a593Smuzhiyun __flush_cache_all();
65*4882a593Smuzhiyun write_c0_wired(0);
66*4882a593Smuzhiyun __asm__("jr %0"::"r"(0xbfc00000));
67*4882a593Smuzhiyun break;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
vr41xx_restart(char * command)71*4882a593Smuzhiyun static void vr41xx_restart(char *command)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun local_irq_disable();
74*4882a593Smuzhiyun software_reset();
75*4882a593Smuzhiyun while (1) ;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
vr41xx_halt(void)78*4882a593Smuzhiyun static void vr41xx_halt(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun local_irq_disable();
81*4882a593Smuzhiyun printk(KERN_NOTICE "\nYou can turn off the power supply\n");
82*4882a593Smuzhiyun __asm__("hibernate;\n");
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
vr41xx_pmu_init(void)85*4882a593Smuzhiyun static int __init vr41xx_pmu_init(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun unsigned long start, size;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun switch (current_cpu_type()) {
90*4882a593Smuzhiyun case CPU_VR4111:
91*4882a593Smuzhiyun case CPU_VR4121:
92*4882a593Smuzhiyun start = PMU_TYPE1_BASE;
93*4882a593Smuzhiyun size = PMU_TYPE1_SIZE;
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun case CPU_VR4122:
96*4882a593Smuzhiyun case CPU_VR4131:
97*4882a593Smuzhiyun case CPU_VR4133:
98*4882a593Smuzhiyun start = PMU_TYPE2_BASE;
99*4882a593Smuzhiyun size = PMU_TYPE2_SIZE;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun default:
102*4882a593Smuzhiyun printk("Unexpected CPU of NEC VR4100 series\n");
103*4882a593Smuzhiyun return -ENODEV;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (request_mem_region(start, size, "PMU") == NULL)
107*4882a593Smuzhiyun return -EBUSY;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun pmu_base = ioremap(start, size);
110*4882a593Smuzhiyun if (pmu_base == NULL) {
111*4882a593Smuzhiyun release_mem_region(start, size);
112*4882a593Smuzhiyun return -EBUSY;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun cpu_wait = vr41xx_cpu_wait;
116*4882a593Smuzhiyun _machine_restart = vr41xx_restart;
117*4882a593Smuzhiyun _machine_halt = vr41xx_halt;
118*4882a593Smuzhiyun pm_power_off = vr41xx_halt;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun core_initcall(vr41xx_pmu_init);
124