1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Toshiba RBTX4939 interrupt routines
3*4882a593Smuzhiyun * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
4*4882a593Smuzhiyun * and RBTX49xx patch from CELF patch archive.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
7*4882a593Smuzhiyun * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8*4882a593Smuzhiyun * terms of the GNU General Public License version 2. This program is
9*4882a593Smuzhiyun * licensed "as is" without any warranty of any kind, whether express
10*4882a593Smuzhiyun * or implied.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <asm/mipsregs.h>
16*4882a593Smuzhiyun #include <asm/txx9/rbtx4939.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * RBTX4939 IOC controller definition
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
rbtx4939_ioc_irq_unmask(struct irq_data * d)22*4882a593Smuzhiyun static void rbtx4939_ioc_irq_unmask(struct irq_data *d)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
rbtx4939_ioc_irq_mask(struct irq_data * d)29*4882a593Smuzhiyun static void rbtx4939_ioc_irq_mask(struct irq_data *d)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
34*4882a593Smuzhiyun mmiowb();
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static struct irq_chip rbtx4939_ioc_irq_chip = {
38*4882a593Smuzhiyun .name = "IOC",
39*4882a593Smuzhiyun .irq_mask = rbtx4939_ioc_irq_mask,
40*4882a593Smuzhiyun .irq_unmask = rbtx4939_ioc_irq_unmask,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun
rbtx4939_ioc_irqroute(void)44*4882a593Smuzhiyun static inline int rbtx4939_ioc_irqroute(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun unsigned char istat = readb(rbtx4939_ifac2_addr);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (unlikely(istat == 0))
49*4882a593Smuzhiyun return -1;
50*4882a593Smuzhiyun return RBTX4939_IRQ_IOC + __fls8(istat);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
rbtx4939_irq_dispatch(int pending)53*4882a593Smuzhiyun static int rbtx4939_irq_dispatch(int pending)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun int irq;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun if (pending & CAUSEF_IP7)
58*4882a593Smuzhiyun return MIPS_CPU_IRQ_BASE + 7;
59*4882a593Smuzhiyun irq = tx4939_irq();
60*4882a593Smuzhiyun if (likely(irq >= 0)) {
61*4882a593Smuzhiyun /* redirect IOC interrupts */
62*4882a593Smuzhiyun switch (irq) {
63*4882a593Smuzhiyun case RBTX4939_IRQ_IOCINT:
64*4882a593Smuzhiyun irq = rbtx4939_ioc_irqroute();
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun } else if (pending & CAUSEF_IP0)
68*4882a593Smuzhiyun irq = MIPS_CPU_IRQ_BASE + 0;
69*4882a593Smuzhiyun else if (pending & CAUSEF_IP1)
70*4882a593Smuzhiyun irq = MIPS_CPU_IRQ_BASE + 1;
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun irq = -1;
73*4882a593Smuzhiyun return irq;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
rbtx4939_irq_setup(void)76*4882a593Smuzhiyun void __init rbtx4939_irq_setup(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun int i;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* mask all IOC interrupts */
81*4882a593Smuzhiyun writeb(0, rbtx4939_ien_addr);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* clear SoftInt interrupts */
84*4882a593Smuzhiyun writeb(0, rbtx4939_softint_addr);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun txx9_irq_dispatch = rbtx4939_irq_dispatch;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun tx4939_irq_init();
89*4882a593Smuzhiyun for (i = RBTX4939_IRQ_IOC;
90*4882a593Smuzhiyun i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
91*4882a593Smuzhiyun irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
92*4882a593Smuzhiyun handle_level_irq);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
95*4882a593Smuzhiyun }
96