1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Toshiba RBTX4938 specific interrupt handlers
3*4882a593Smuzhiyun * Copyright (C) 2000-2001 Toshiba Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6*4882a593Smuzhiyun * terms of the GNU General Public License version 2. This program is
7*4882a593Smuzhiyun * licensed "as is" without any warranty of any kind, whether express
8*4882a593Smuzhiyun * or implied.
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+00 Software 0
15*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+01 Software 1
16*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
17*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
18*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
19*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
20*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
21*4882a593Smuzhiyun * MIPS_CPU_IRQ_BASE+07 CPU TIMER
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * TXX9_IRQ_BASE+00
24*4882a593Smuzhiyun * TXX9_IRQ_BASE+01
25*4882a593Smuzhiyun * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
26*4882a593Smuzhiyun * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
27*4882a593Smuzhiyun * TXX9_IRQ_BASE+04
28*4882a593Smuzhiyun * TXX9_IRQ_BASE+05 TX4938 ETH1
29*4882a593Smuzhiyun * TXX9_IRQ_BASE+06 TX4938 ETH0
30*4882a593Smuzhiyun * TXX9_IRQ_BASE+07
31*4882a593Smuzhiyun * TXX9_IRQ_BASE+08 TX4938 SIO 0
32*4882a593Smuzhiyun * TXX9_IRQ_BASE+09 TX4938 SIO 1
33*4882a593Smuzhiyun * TXX9_IRQ_BASE+10 TX4938 DMA0
34*4882a593Smuzhiyun * TXX9_IRQ_BASE+11 TX4938 DMA1
35*4882a593Smuzhiyun * TXX9_IRQ_BASE+12 TX4938 DMA2
36*4882a593Smuzhiyun * TXX9_IRQ_BASE+13 TX4938 DMA3
37*4882a593Smuzhiyun * TXX9_IRQ_BASE+14
38*4882a593Smuzhiyun * TXX9_IRQ_BASE+15
39*4882a593Smuzhiyun * TXX9_IRQ_BASE+16 TX4938 PCIC
40*4882a593Smuzhiyun * TXX9_IRQ_BASE+17 TX4938 TMR0
41*4882a593Smuzhiyun * TXX9_IRQ_BASE+18 TX4938 TMR1
42*4882a593Smuzhiyun * TXX9_IRQ_BASE+19 TX4938 TMR2
43*4882a593Smuzhiyun * TXX9_IRQ_BASE+20
44*4882a593Smuzhiyun * TXX9_IRQ_BASE+21
45*4882a593Smuzhiyun * TXX9_IRQ_BASE+22 TX4938 PCIERR
46*4882a593Smuzhiyun * TXX9_IRQ_BASE+23
47*4882a593Smuzhiyun * TXX9_IRQ_BASE+24
48*4882a593Smuzhiyun * TXX9_IRQ_BASE+25
49*4882a593Smuzhiyun * TXX9_IRQ_BASE+26
50*4882a593Smuzhiyun * TXX9_IRQ_BASE+27
51*4882a593Smuzhiyun * TXX9_IRQ_BASE+28
52*4882a593Smuzhiyun * TXX9_IRQ_BASE+29
53*4882a593Smuzhiyun * TXX9_IRQ_BASE+30
54*4882a593Smuzhiyun * TXX9_IRQ_BASE+31 TX4938 SPI
55*4882a593Smuzhiyun *
56*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+00 PCI-D
57*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+01 PCI-C
58*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+02 PCI-B
59*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+03 PCI-A
60*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+04 RTC
61*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+05 ATA
62*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+06 MODEM
63*4882a593Smuzhiyun * RBTX4938_IRQ_IOC+07 SWINT
64*4882a593Smuzhiyun */
65*4882a593Smuzhiyun #include <linux/init.h>
66*4882a593Smuzhiyun #include <linux/interrupt.h>
67*4882a593Smuzhiyun #include <linux/irq.h>
68*4882a593Smuzhiyun #include <asm/mipsregs.h>
69*4882a593Smuzhiyun #include <asm/txx9/generic.h>
70*4882a593Smuzhiyun #include <asm/txx9/rbtx4938.h>
71*4882a593Smuzhiyun
toshiba_rbtx4938_irq_nested(int sw_irq)72*4882a593Smuzhiyun static int toshiba_rbtx4938_irq_nested(int sw_irq)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun u8 level3;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun level3 = readb(rbtx4938_imstat_addr);
77*4882a593Smuzhiyun if (unlikely(!level3))
78*4882a593Smuzhiyun return -1;
79*4882a593Smuzhiyun /* must use fls so onboard ATA has priority */
80*4882a593Smuzhiyun return RBTX4938_IRQ_IOC + __fls8(level3);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
toshiba_rbtx4938_irq_ioc_enable(struct irq_data * d)83*4882a593Smuzhiyun static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun unsigned char v;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun v = readb(rbtx4938_imask_addr);
88*4882a593Smuzhiyun v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
89*4882a593Smuzhiyun writeb(v, rbtx4938_imask_addr);
90*4882a593Smuzhiyun mmiowb();
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
toshiba_rbtx4938_irq_ioc_disable(struct irq_data * d)93*4882a593Smuzhiyun static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun unsigned char v;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun v = readb(rbtx4938_imask_addr);
98*4882a593Smuzhiyun v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
99*4882a593Smuzhiyun writeb(v, rbtx4938_imask_addr);
100*4882a593Smuzhiyun mmiowb();
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
104*4882a593Smuzhiyun static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
105*4882a593Smuzhiyun .name = TOSHIBA_RBTX4938_IOC_NAME,
106*4882a593Smuzhiyun .irq_mask = toshiba_rbtx4938_irq_ioc_disable,
107*4882a593Smuzhiyun .irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
rbtx4938_irq_dispatch(int pending)110*4882a593Smuzhiyun static int rbtx4938_irq_dispatch(int pending)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun int irq;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (pending & STATUSF_IP7)
115*4882a593Smuzhiyun irq = MIPS_CPU_IRQ_BASE + 7;
116*4882a593Smuzhiyun else if (pending & STATUSF_IP2) {
117*4882a593Smuzhiyun irq = txx9_irq();
118*4882a593Smuzhiyun if (irq == RBTX4938_IRQ_IOCINT)
119*4882a593Smuzhiyun irq = toshiba_rbtx4938_irq_nested(irq);
120*4882a593Smuzhiyun } else if (pending & STATUSF_IP1)
121*4882a593Smuzhiyun irq = MIPS_CPU_IRQ_BASE + 0;
122*4882a593Smuzhiyun else if (pending & STATUSF_IP0)
123*4882a593Smuzhiyun irq = MIPS_CPU_IRQ_BASE + 1;
124*4882a593Smuzhiyun else
125*4882a593Smuzhiyun irq = -1;
126*4882a593Smuzhiyun return irq;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
toshiba_rbtx4938_irq_ioc_init(void)129*4882a593Smuzhiyun static void __init toshiba_rbtx4938_irq_ioc_init(void)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun int i;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun for (i = RBTX4938_IRQ_IOC;
134*4882a593Smuzhiyun i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
135*4882a593Smuzhiyun irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
136*4882a593Smuzhiyun handle_level_irq);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
rbtx4938_irq_setup(void)141*4882a593Smuzhiyun void __init rbtx4938_irq_setup(void)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun txx9_irq_dispatch = rbtx4938_irq_dispatch;
144*4882a593Smuzhiyun /* Now, interrupt control disabled, */
145*4882a593Smuzhiyun /* all IRC interrupts are masked, */
146*4882a593Smuzhiyun /* all IRC interrupt mode are Low Active. */
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* mask all IOC interrupts */
149*4882a593Smuzhiyun writeb(0, rbtx4938_imask_addr);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* clear SoftInt interrupts */
152*4882a593Smuzhiyun writeb(0, rbtx4938_softint_addr);
153*4882a593Smuzhiyun tx4938_irq_init();
154*4882a593Smuzhiyun toshiba_rbtx4938_irq_ioc_init();
155*4882a593Smuzhiyun /* Onboard 10M Ether: High Active */
156*4882a593Smuzhiyun irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
157*4882a593Smuzhiyun }
158