xref: /OK3568_Linux_fs/kernel/arch/mips/sni/pcit.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * PCI Tower specific code
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General Public
5*4882a593Smuzhiyun  * License.  See the file "COPYING" in the main directory of this archive
6*4882a593Smuzhiyun  * for more details.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/serial_8250.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <asm/sni.h>
18*4882a593Smuzhiyun #include <asm/time.h>
19*4882a593Smuzhiyun #include <asm/irq_cpu.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define PORT(_base,_irq)				\
23*4882a593Smuzhiyun 	{						\
24*4882a593Smuzhiyun 		.iobase		= _base,		\
25*4882a593Smuzhiyun 		.irq		= _irq,			\
26*4882a593Smuzhiyun 		.uartclk	= 1843200,		\
27*4882a593Smuzhiyun 		.iotype		= UPIO_PORT,		\
28*4882a593Smuzhiyun 		.flags		= UPF_BOOT_AUTOCONF,	\
29*4882a593Smuzhiyun 	}
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun static struct plat_serial8250_port pcit_data[] = {
32*4882a593Smuzhiyun 	PORT(0x3f8, 0),
33*4882a593Smuzhiyun 	PORT(0x2f8, 3),
34*4882a593Smuzhiyun 	{ },
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun static struct platform_device pcit_serial8250_device = {
38*4882a593Smuzhiyun 	.name			= "serial8250",
39*4882a593Smuzhiyun 	.id			= PLAT8250_DEV_PLATFORM,
40*4882a593Smuzhiyun 	.dev			= {
41*4882a593Smuzhiyun 		.platform_data	= pcit_data,
42*4882a593Smuzhiyun 	},
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static struct plat_serial8250_port pcit_cplus_data[] = {
46*4882a593Smuzhiyun 	PORT(0x3f8, 0),
47*4882a593Smuzhiyun 	PORT(0x2f8, 3),
48*4882a593Smuzhiyun 	PORT(0x3e8, 4),
49*4882a593Smuzhiyun 	PORT(0x2e8, 3),
50*4882a593Smuzhiyun 	{ },
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static struct platform_device pcit_cplus_serial8250_device = {
54*4882a593Smuzhiyun 	.name			= "serial8250",
55*4882a593Smuzhiyun 	.id			= PLAT8250_DEV_PLATFORM,
56*4882a593Smuzhiyun 	.dev			= {
57*4882a593Smuzhiyun 		.platform_data	= pcit_cplus_data,
58*4882a593Smuzhiyun 	},
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static struct resource pcit_cmos_rsrc[] = {
62*4882a593Smuzhiyun 	{
63*4882a593Smuzhiyun 		.start = 0x70,
64*4882a593Smuzhiyun 		.end   = 0x71,
65*4882a593Smuzhiyun 		.flags = IORESOURCE_IO
66*4882a593Smuzhiyun 	},
67*4882a593Smuzhiyun 	{
68*4882a593Smuzhiyun 		.start = 8,
69*4882a593Smuzhiyun 		.end   = 8,
70*4882a593Smuzhiyun 		.flags = IORESOURCE_IRQ
71*4882a593Smuzhiyun 	}
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static struct platform_device pcit_cmos_device = {
75*4882a593Smuzhiyun 	.name		= "rtc_cmos",
76*4882a593Smuzhiyun 	.num_resources	= ARRAY_SIZE(pcit_cmos_rsrc),
77*4882a593Smuzhiyun 	.resource	= pcit_cmos_rsrc
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static struct platform_device pcit_pcspeaker_pdev = {
81*4882a593Smuzhiyun 	.name		= "pcspkr",
82*4882a593Smuzhiyun 	.id		= -1,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun static struct resource sni_io_resource = {
86*4882a593Smuzhiyun 	.start	= 0x00000000UL,
87*4882a593Smuzhiyun 	.end	= 0x03bfffffUL,
88*4882a593Smuzhiyun 	.name	= "PCIT IO",
89*4882a593Smuzhiyun 	.flags	= IORESOURCE_IO,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun static struct resource pcit_io_resources[] = {
93*4882a593Smuzhiyun 	{
94*4882a593Smuzhiyun 		.start	= 0x00,
95*4882a593Smuzhiyun 		.end	= 0x1f,
96*4882a593Smuzhiyun 		.name	= "dma1",
97*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
98*4882a593Smuzhiyun 	}, {
99*4882a593Smuzhiyun 		.start	=  0x40,
100*4882a593Smuzhiyun 		.end	= 0x5f,
101*4882a593Smuzhiyun 		.name	= "timer",
102*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
103*4882a593Smuzhiyun 	}, {
104*4882a593Smuzhiyun 		.start	=  0x60,
105*4882a593Smuzhiyun 		.end	= 0x6f,
106*4882a593Smuzhiyun 		.name	= "keyboard",
107*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
108*4882a593Smuzhiyun 	}, {
109*4882a593Smuzhiyun 		.start	=  0x80,
110*4882a593Smuzhiyun 		.end	= 0x8f,
111*4882a593Smuzhiyun 		.name	= "dma page reg",
112*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
113*4882a593Smuzhiyun 	}, {
114*4882a593Smuzhiyun 		.start	=  0xc0,
115*4882a593Smuzhiyun 		.end	= 0xdf,
116*4882a593Smuzhiyun 		.name	= "dma2",
117*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
118*4882a593Smuzhiyun 	}, {
119*4882a593Smuzhiyun 		.start	=  0xcf8,
120*4882a593Smuzhiyun 		.end	= 0xcfb,
121*4882a593Smuzhiyun 		.name	= "PCI config addr",
122*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
123*4882a593Smuzhiyun 	}, {
124*4882a593Smuzhiyun 		.start	=  0xcfc,
125*4882a593Smuzhiyun 		.end	= 0xcff,
126*4882a593Smuzhiyun 		.name	= "PCI config data",
127*4882a593Smuzhiyun 		.flags	= IORESOURCE_BUSY
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
sni_pcit_resource_init(void)131*4882a593Smuzhiyun static void __init sni_pcit_resource_init(void)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	int i;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* request I/O space for devices used on all i[345]86 PCs */
136*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
137*4882a593Smuzhiyun 		request_resource(&sni_io_resource, pcit_io_resources + i);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun extern struct pci_ops sni_pcit_ops;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #ifdef CONFIG_PCI
144*4882a593Smuzhiyun static struct resource sni_mem_resource = {
145*4882a593Smuzhiyun 	.start	= 0x18000000UL,
146*4882a593Smuzhiyun 	.end	= 0x1fbfffffUL,
147*4882a593Smuzhiyun 	.name	= "PCIT PCI MEM",
148*4882a593Smuzhiyun 	.flags	= IORESOURCE_MEM
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static struct pci_controller sni_pcit_controller = {
152*4882a593Smuzhiyun 	.pci_ops	= &sni_pcit_ops,
153*4882a593Smuzhiyun 	.mem_resource	= &sni_mem_resource,
154*4882a593Smuzhiyun 	.mem_offset	= 0x00000000UL,
155*4882a593Smuzhiyun 	.io_resource	= &sni_io_resource,
156*4882a593Smuzhiyun 	.io_offset	= 0x00000000UL,
157*4882a593Smuzhiyun 	.io_map_base	= SNI_PORT_BASE
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun #endif /* CONFIG_PCI */
160*4882a593Smuzhiyun 
enable_pcit_irq(struct irq_data * d)161*4882a593Smuzhiyun static void enable_pcit_irq(struct irq_data *d)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	*(volatile u32 *)SNI_PCIT_INT_REG |= mask;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
disable_pcit_irq(struct irq_data * d)168*4882a593Smuzhiyun void disable_pcit_irq(struct irq_data *d)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static struct irq_chip pcit_irq_type = {
176*4882a593Smuzhiyun 	.name = "PCIT",
177*4882a593Smuzhiyun 	.irq_mask = disable_pcit_irq,
178*4882a593Smuzhiyun 	.irq_unmask = enable_pcit_irq,
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
pcit_hwint1(void)181*4882a593Smuzhiyun static void pcit_hwint1(void)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
184*4882a593Smuzhiyun 	int irq;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	clear_c0_status(IE_IRQ1);
187*4882a593Smuzhiyun 	irq = ffs((pending >> 16) & 0x7f);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	if (likely(irq > 0))
190*4882a593Smuzhiyun 		do_IRQ(irq + SNI_PCIT_INT_START - 1);
191*4882a593Smuzhiyun 	set_c0_status(IE_IRQ1);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
pcit_hwint0(void)194*4882a593Smuzhiyun static void pcit_hwint0(void)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
197*4882a593Smuzhiyun 	int irq;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	clear_c0_status(IE_IRQ0);
200*4882a593Smuzhiyun 	irq = ffs((pending >> 16) & 0x3f);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	if (likely(irq > 0))
203*4882a593Smuzhiyun 		do_IRQ(irq + SNI_PCIT_INT_START - 1);
204*4882a593Smuzhiyun 	set_c0_status(IE_IRQ0);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
sni_pcit_hwint(void)207*4882a593Smuzhiyun static void sni_pcit_hwint(void)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	u32 pending = read_c0_cause() & read_c0_status();
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (pending & C_IRQ1)
212*4882a593Smuzhiyun 		pcit_hwint1();
213*4882a593Smuzhiyun 	else if (pending & C_IRQ2)
214*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
215*4882a593Smuzhiyun 	else if (pending & C_IRQ3)
216*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
217*4882a593Smuzhiyun 	else if (pending & C_IRQ5)
218*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
sni_pcit_hwint_cplus(void)221*4882a593Smuzhiyun static void sni_pcit_hwint_cplus(void)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	u32 pending = read_c0_cause() & read_c0_status();
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	if (pending & C_IRQ0)
226*4882a593Smuzhiyun 		pcit_hwint0();
227*4882a593Smuzhiyun 	else if (pending & C_IRQ1)
228*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 3);
229*4882a593Smuzhiyun 	else if (pending & C_IRQ2)
230*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
231*4882a593Smuzhiyun 	else if (pending & C_IRQ3)
232*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
233*4882a593Smuzhiyun 	else if (pending & C_IRQ5)
234*4882a593Smuzhiyun 		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
sni_pcit_irq_init(void)237*4882a593Smuzhiyun void __init sni_pcit_irq_init(void)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	int i;
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	mips_cpu_irq_init();
242*4882a593Smuzhiyun 	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
243*4882a593Smuzhiyun 		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
244*4882a593Smuzhiyun 	*(volatile u32 *)SNI_PCIT_INT_REG = 0;
245*4882a593Smuzhiyun 	sni_hwint = sni_pcit_hwint;
246*4882a593Smuzhiyun 	change_c0_status(ST0_IM, IE_IRQ1);
247*4882a593Smuzhiyun 	if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler, 0, "ISA",
248*4882a593Smuzhiyun 			NULL))
249*4882a593Smuzhiyun 		pr_err("Failed to register ISA interrupt\n");
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun 
sni_pcit_cplus_irq_init(void)252*4882a593Smuzhiyun void __init sni_pcit_cplus_irq_init(void)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	int i;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	mips_cpu_irq_init();
257*4882a593Smuzhiyun 	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
258*4882a593Smuzhiyun 		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
259*4882a593Smuzhiyun 	*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
260*4882a593Smuzhiyun 	sni_hwint = sni_pcit_hwint_cplus;
261*4882a593Smuzhiyun 	change_c0_status(ST0_IM, IE_IRQ0);
262*4882a593Smuzhiyun 	if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
263*4882a593Smuzhiyun 			NULL))
264*4882a593Smuzhiyun 		pr_err("Failed to register ISA interrupt\n");
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
sni_pcit_init(void)267*4882a593Smuzhiyun void __init sni_pcit_init(void)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	ioport_resource.end = sni_io_resource.end;
270*4882a593Smuzhiyun #ifdef CONFIG_PCI
271*4882a593Smuzhiyun 	PCIBIOS_MIN_IO = 0x9000;
272*4882a593Smuzhiyun 	register_pci_controller(&sni_pcit_controller);
273*4882a593Smuzhiyun #endif
274*4882a593Smuzhiyun 	sni_pcit_resource_init();
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
snirm_pcit_setup_devinit(void)277*4882a593Smuzhiyun static int __init snirm_pcit_setup_devinit(void)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	switch (sni_brd_type) {
280*4882a593Smuzhiyun 	case SNI_BRD_PCI_TOWER:
281*4882a593Smuzhiyun 		platform_device_register(&pcit_serial8250_device);
282*4882a593Smuzhiyun 		platform_device_register(&pcit_cmos_device);
283*4882a593Smuzhiyun 		platform_device_register(&pcit_pcspeaker_pdev);
284*4882a593Smuzhiyun 		break;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	case SNI_BRD_PCI_TOWER_CPLUS:
287*4882a593Smuzhiyun 		platform_device_register(&pcit_cplus_serial8250_device);
288*4882a593Smuzhiyun 		platform_device_register(&pcit_cmos_device);
289*4882a593Smuzhiyun 		platform_device_register(&pcit_pcspeaker_pdev);
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 	}
292*4882a593Smuzhiyun 	return 0;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun device_initcall(snirm_pcit_setup_devinit);
296