xref: /OK3568_Linux_fs/kernel/arch/mips/sibyte/sb1250/smp.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/init.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/smp.h>
10*4882a593Smuzhiyun #include <linux/kernel_stat.h>
11*4882a593Smuzhiyun #include <linux/sched/task_stack.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <asm/mmu_context.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/fw/cfe/cfe_api.h>
16*4882a593Smuzhiyun #include <asm/sibyte/sb1250.h>
17*4882a593Smuzhiyun #include <asm/sibyte/sb1250_regs.h>
18*4882a593Smuzhiyun #include <asm/sibyte/sb1250_int.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static void *mailbox_set_regs[] = {
21*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
22*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun static void *mailbox_clear_regs[] = {
26*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
27*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun static void *mailbox_regs[] = {
31*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
32*4882a593Smuzhiyun 	IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * SMP init and finish on secondary CPUs
37*4882a593Smuzhiyun  */
sb1250_smp_init(void)38*4882a593Smuzhiyun void sb1250_smp_init(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
41*4882a593Smuzhiyun 		STATUSF_IP1 | STATUSF_IP0;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	/* Set interrupt mask, but don't enable */
44*4882a593Smuzhiyun 	change_c0_status(ST0_IM, imask);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun  * These are routines for dealing with the sb1250 smp capabilities
49*4882a593Smuzhiyun  * independent of board/firmware
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun  * Simple enough; everything is set up, so just poke the appropriate mailbox
54*4882a593Smuzhiyun  * register, and we should be set
55*4882a593Smuzhiyun  */
sb1250_send_ipi_single(int cpu,unsigned int action)56*4882a593Smuzhiyun static void sb1250_send_ipi_single(int cpu, unsigned int action)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	__raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
sb1250_send_ipi_mask(const struct cpumask * mask,unsigned int action)61*4882a593Smuzhiyun static inline void sb1250_send_ipi_mask(const struct cpumask *mask,
62*4882a593Smuzhiyun 					unsigned int action)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	unsigned int i;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	for_each_cpu(i, mask)
67*4882a593Smuzhiyun 		sb1250_send_ipi_single(i, action);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun  * Code to run on secondary just after probing the CPU
72*4882a593Smuzhiyun  */
sb1250_init_secondary(void)73*4882a593Smuzhiyun static void sb1250_init_secondary(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	extern void sb1250_smp_init(void);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	sb1250_smp_init();
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun  * Do any tidying up before marking online and running the idle
82*4882a593Smuzhiyun  * loop
83*4882a593Smuzhiyun  */
sb1250_smp_finish(void)84*4882a593Smuzhiyun static void sb1250_smp_finish(void)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	extern void sb1250_clockevent_init(void);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	sb1250_clockevent_init();
89*4882a593Smuzhiyun 	local_irq_enable();
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun  * Setup the PC, SP, and GP of a secondary processor and start it
94*4882a593Smuzhiyun  * running!
95*4882a593Smuzhiyun  */
sb1250_boot_secondary(int cpu,struct task_struct * idle)96*4882a593Smuzhiyun static int sb1250_boot_secondary(int cpu, struct task_struct *idle)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	int retval;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
101*4882a593Smuzhiyun 			       __KSTK_TOS(idle),
102*4882a593Smuzhiyun 			       (unsigned long)task_thread_info(idle), 0);
103*4882a593Smuzhiyun 	if (retval != 0)
104*4882a593Smuzhiyun 		printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
105*4882a593Smuzhiyun 	return retval;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun  * Use CFE to find out how many CPUs are available, setting up
110*4882a593Smuzhiyun  * cpu_possible_mask and the logical/physical mappings.
111*4882a593Smuzhiyun  * XXXKW will the boot CPU ever not be physical 0?
112*4882a593Smuzhiyun  *
113*4882a593Smuzhiyun  * Common setup before any secondaries are started
114*4882a593Smuzhiyun  */
sb1250_smp_setup(void)115*4882a593Smuzhiyun static void __init sb1250_smp_setup(void)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	int i, num;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	init_cpu_possible(cpumask_of(0));
120*4882a593Smuzhiyun 	__cpu_number_map[0] = 0;
121*4882a593Smuzhiyun 	__cpu_logical_map[0] = 0;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	for (i = 1, num = 0; i < NR_CPUS; i++) {
124*4882a593Smuzhiyun 		if (cfe_cpu_stop(i) == 0) {
125*4882a593Smuzhiyun 			set_cpu_possible(i, true);
126*4882a593Smuzhiyun 			__cpu_number_map[i] = ++num;
127*4882a593Smuzhiyun 			__cpu_logical_map[num] = i;
128*4882a593Smuzhiyun 		}
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
sb1250_prepare_cpus(unsigned int max_cpus)133*4882a593Smuzhiyun static void __init sb1250_prepare_cpus(unsigned int max_cpus)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun const struct plat_smp_ops sb_smp_ops = {
138*4882a593Smuzhiyun 	.send_ipi_single	= sb1250_send_ipi_single,
139*4882a593Smuzhiyun 	.send_ipi_mask		= sb1250_send_ipi_mask,
140*4882a593Smuzhiyun 	.init_secondary		= sb1250_init_secondary,
141*4882a593Smuzhiyun 	.smp_finish		= sb1250_smp_finish,
142*4882a593Smuzhiyun 	.boot_secondary		= sb1250_boot_secondary,
143*4882a593Smuzhiyun 	.smp_setup		= sb1250_smp_setup,
144*4882a593Smuzhiyun 	.prepare_cpus		= sb1250_prepare_cpus,
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
sb1250_mailbox_interrupt(void)147*4882a593Smuzhiyun void sb1250_mailbox_interrupt(void)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	int cpu = smp_processor_id();
150*4882a593Smuzhiyun 	int irq = K_INT_MBOX_0;
151*4882a593Smuzhiyun 	unsigned int action;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	kstat_incr_irq_this_cpu(irq);
154*4882a593Smuzhiyun 	/* Load the mailbox register to figure out what we're supposed to do */
155*4882a593Smuzhiyun 	action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	/* Clear the mailbox to clear the interrupt */
158*4882a593Smuzhiyun 	____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	if (action & SMP_RESCHEDULE_YOURSELF)
161*4882a593Smuzhiyun 		scheduler_ipi();
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (action & SMP_CALL_FUNCTION) {
164*4882a593Smuzhiyun 		irq_enter();
165*4882a593Smuzhiyun 		generic_smp_call_function_interrupt();
166*4882a593Smuzhiyun 		irq_exit();
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun }
169