1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #include <linux/dma-direct.h> 6*4882a593Smuzhiyun #include <asm/ip32/crime.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Few notes. 10*4882a593Smuzhiyun * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M 11*4882a593Smuzhiyun * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for 12*4882a593Smuzhiyun * native-endian) 13*4882a593Smuzhiyun * 3. All other devices see memory as one big chunk at 0x40000000 14*4882a593Smuzhiyun * 4. Non-PCI devices will pass NULL as struct device* 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Thus we translate differently, depending on device. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RAM_OFFSET_MASK 0x3fffffffUL 20*4882a593Smuzhiyun phys_to_dma(struct device * dev,phys_addr_t paddr)21*4882a593Smuzhiyundma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun dma_addr_t dma_addr = paddr & RAM_OFFSET_MASK; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun if (!dev) 26*4882a593Smuzhiyun dma_addr += CRIME_HI_MEM_BASE; 27*4882a593Smuzhiyun return dma_addr; 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun dma_to_phys(struct device * dev,dma_addr_t dma_addr)30*4882a593Smuzhiyunphys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun phys_addr_t paddr = dma_addr & RAM_OFFSET_MASK; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun if (dma_addr >= 256*1024*1024) 35*4882a593Smuzhiyun paddr += CRIME_HI_MEM_BASE; 36*4882a593Smuzhiyun return paddr; 37*4882a593Smuzhiyun } 38