1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ip30-timer.c: Clocksource/clockevent support for the
4*4882a593Smuzhiyun * HEART chip in SGI Octane (IP30) systems.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7*4882a593Smuzhiyun * Copyright (C) 2009 Johannes Dickgreber <tanzy@gmx.de>
8*4882a593Smuzhiyun * Copyright (C) 2011 Joshua Kinard <kumba@gentoo.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clocksource.h>
12*4882a593Smuzhiyun #include <linux/cpumask.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/percpu.h>
16*4882a593Smuzhiyun #include <linux/sched_clock.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/time.h>
19*4882a593Smuzhiyun #include <asm/cevt-r4k.h>
20*4882a593Smuzhiyun #include <asm/sgi/heart.h>
21*4882a593Smuzhiyun
ip30_heart_counter_read(struct clocksource * cs)22*4882a593Smuzhiyun static u64 ip30_heart_counter_read(struct clocksource *cs)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return heart_read(&heart_regs->count);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct clocksource ip30_heart_clocksource = {
28*4882a593Smuzhiyun .name = "HEART",
29*4882a593Smuzhiyun .rating = 400,
30*4882a593Smuzhiyun .read = ip30_heart_counter_read,
31*4882a593Smuzhiyun .mask = CLOCKSOURCE_MASK(52),
32*4882a593Smuzhiyun .flags = (CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_VALID_FOR_HRES),
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
ip30_heart_read_sched_clock(void)35*4882a593Smuzhiyun static u64 notrace ip30_heart_read_sched_clock(void)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun return heart_read(&heart_regs->count);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
ip30_heart_clocksource_init(void)40*4882a593Smuzhiyun static void __init ip30_heart_clocksource_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct clocksource *cs = &ip30_heart_clocksource;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun clocksource_register_hz(cs, HEART_CYCLES_PER_SEC);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun sched_clock_register(ip30_heart_read_sched_clock, 52,
47*4882a593Smuzhiyun HEART_CYCLES_PER_SEC);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
plat_time_init(void)50*4882a593Smuzhiyun void __init plat_time_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int irq = get_c0_compare_int();
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun cp0_timer_irq_installed = 1;
55*4882a593Smuzhiyun c0_compare_irqaction.percpu_dev_id = &mips_clockevent_device;
56*4882a593Smuzhiyun c0_compare_irqaction.flags &= ~IRQF_SHARED;
57*4882a593Smuzhiyun irq_set_handler(irq, handle_percpu_devid_irq);
58*4882a593Smuzhiyun irq_set_percpu_devid(irq);
59*4882a593Smuzhiyun setup_percpu_irq(irq, &c0_compare_irqaction);
60*4882a593Smuzhiyun enable_percpu_irq(irq, IRQ_TYPE_NONE);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ip30_heart_clocksource_init();
63*4882a593Smuzhiyun }
64